公开(公告)号：US07248494B2

公开(公告)日：2007-07-24

申请号：US11220294

申请日：2005-09-06

申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

公开(公告)号：US20140169069A1

公开(公告)日：2014-06-19

申请号：US14094021

申请日：2013-12-02

申请人： Hyung-Rok Oh

发明人： Hyung-Rok Oh

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/22 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0071 ,  G11C2213/79

摘要： A resistive memory device includes a memory cell array, a memory interface and a read sensing circuit. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of wordlines and a plurality of bitlines. The memory interface is configured to communicate with a memory controller. The read sensing circuit is coupled to the bitlines and includes at least one sensing node. The read sensing circuit performs a precharge operation to precharge the at least one sensing node between a first time point of receiving an active command through the memory interface and a second time point of receiving a read command through the memory interface, and senses data stored in the resistive memory cells to provide read data.

摘要翻译： 电阻式存储器件包括存储单元阵列，存储器接口和读取感测电路。 存储单元阵列包括耦合到多个字线和多个位线的多个电阻存储器单元。 存储器接口被配置为与存储器控制器通信。 读取感测电路耦合到位线并且包括至少一个感测节点。 读取感测电路执行预充电操作，以在通过存储器接口接收活动命令的第一时间点和通过存储器接口接收读取命令的第二时间点之间对至少一个感测节点进行预充电，并且感测存储在 电阻存储单元提供读数据。

公开(公告)号：US20100090213A1

公开(公告)日：2010-04-15

申请号：US12638599

申请日：2009-12-15

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

IPC分类号： H01L29/18

CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C17/165

摘要： A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

摘要翻译： 提供了一种编程一次性可编程器件的方法。 设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断保险丝。 保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。 还公开了相关的一次性可编程器件，相变存储器件和电子系统。

公开(公告)号：US20060050548A1

公开(公告)日：2006-03-09

申请号：US11220294

申请日：2005-09-06

申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

公开(公告)号：US07405960B2

公开(公告)日：2008-07-29

申请号：US11695232

申请日：2007-04-02

申请人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

发明人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

摘要： A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

摘要翻译： 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

公开(公告)号：US20080112208A1

公开(公告)日：2008-05-15

申请号：US11695232

申请日：2007-04-02

申请人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

发明人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

IPC分类号： G11C11/34 ,  G11C11/00 ,  G11C5/06

CPC分类号： G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

摘要： A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

摘要翻译： 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

公开(公告)号：US20080007986A1

公开(公告)日：2008-01-10

申请号：US11564751

申请日：2006-11-29

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C17/165

摘要： A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

摘要翻译： 提供了一种编程一次性可编程器件的方法。 设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断保险丝。 保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。 还公开了相关的一次性可编程器件，相变存储器件和电子系统。

公开(公告)号：US20120182786A1

公开(公告)日：2012-07-19

申请号：US13349167

申请日：2012-01-12

申请人： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

发明人： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

IPC分类号： G11C11/21

CPC分类号： G11C13/004 ,  G11C8/10 ,  G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

摘要： A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.

摘要翻译： 存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性 并将所确定的极性的读取电压施加到所选存储单元。 输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

公开(公告)号：US07974115B2

公开(公告)日：2011-07-05

申请号：US12638599

申请日：2009-12-15

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C17/165

摘要： A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to a switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes.

摘要翻译： 设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断熔丝。 保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。

公开(公告)号：US07869271B2

公开(公告)日：2011-01-11

申请号：US12787571

申请日：2010-05-26

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。