公开(公告)号：US07405960B2

公开(公告)日：2008-07-29

申请号：US11695232

申请日：2007-04-02

申请人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

发明人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

摘要： A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

摘要翻译： 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

公开(公告)号：US20080112208A1

公开(公告)日：2008-05-15

申请号：US11695232

申请日：2007-04-02

申请人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

发明人： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

IPC分类号： G11C11/34 ,  G11C11/00 ,  G11C5/06

CPC分类号： G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

摘要： A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

摘要翻译： 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US07869271B2

公开(公告)日：2011-01-11

申请号：US12787571

申请日：2010-05-26

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US09291868B2

公开(公告)日：2016-03-22

申请号：US13242875

申请日：2011-09-23

申请人： Chang-Soo Lee ,  Kee-Bum Park ,  Yun Jae Park ,  Jong Jae Lee ,  Hoi Sik Moon

发明人： Chang-Soo Lee ,  Kee-Bum Park ,  Yun Jae Park ,  Jong Jae Lee ,  Hoi Sik Moon

IPC分类号： G02F1/136 ,  G02F1/1343 ,  G02F1/1362 ,  H01L29/417

CPC分类号： G02F1/1362 ,  G02F1/13624 ,  G02F1/136286 ,  H01L29/41733

摘要： A liquid crystal display includes a plurality of pixels arranged in a matrix, each pixel having a first sub-pixel electrode and a second sub-pixel electrode. A first thin film transistor is connected to the first sub-pixel electrode. A second thin film transistor is connected to the second sub-pixel electrode. A third thin film transistor is connected to the second sub-pixel electrode. A fourth thin film transistor is connected to a drain electrode of the third thin film transistor. A first gate line is connected to the first thin film transistor and the second thin film transistor. A data line is connected to the first thin film transistor and the second thin film transistor. A second gate line is connected to the third thin film transistor. A third gate line is connected to the fourth thin film transistor.

摘要翻译： 液晶显示器包括以矩阵排列的多个像素，每个像素具有第一子像素电极和第二子像素电极。 第一薄膜晶体管连接到第一子像素电极。 第二薄膜晶体管连接到第二子像素电极。 第三薄膜晶体管连接到第二子像素电极。 第四薄膜晶体管连接到第三薄膜晶体管的漏电极。 第一栅极线连接到第一薄膜晶体管和第二薄膜晶体管。 数据线连接到第一薄膜晶体管和第二薄膜晶体管。 第二栅极线连接到第三薄膜晶体管。 第三栅极线连接到第四薄膜晶体管。

公开(公告)号：US09053661B2

公开(公告)日：2015-06-09

申请号：US13102076

申请日：2011-05-06

申请人： Chang-Soo Lee ,  Jong Jae Lee

发明人： Chang-Soo Lee ,  Jong Jae Lee

IPC分类号： G09G5/00 ,  G09G3/20 ,  G09G3/32 ,  G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0267

摘要： A gate-off voltage generator provides a gate-off voltage to a gate line of a display panel. The gate-off voltage generator includes a transistor having a base terminal, a collector terminal, and an emitter terminal, the emitter terminal configured to output the gate-off voltage to the gate line. A controller is connected to the base terminal. A feedback circuit is connected between the gate line and the controller, the feedback circuit configured to provide to the controller a feedback voltage based upon the gate-off voltage outputted from the emitter terminal. The gate-off voltage from the emitter terminal is compared with a desired gate-off voltage in the controller and the voltage at the base terminal is controlled by the controller to provide the desired gate-off voltage to gate line.

摘要翻译： 栅极截止电压发生器向显示面板的栅极线提供栅极截止电压。 栅极截止电压发生器包括具有基极端子，集电极端子和发射极端子的晶体管，发射极端子被配置为将栅极截止电压输出到栅极线。 控制器连接到基本终端。 反馈电路连接在栅极线和控制器之间，反馈电路被配置为基于从发射极端子输出的栅极截止电压向控制器提供反馈电压。 将来自发射极端子的栅极截止电压与控制器中的期望栅极截止电压进行比较，并且由控制器控制基极端子处的电压，以向栅极线提供所需的栅极截止电压。

公开(公告)号：US08779183B2

公开(公告)日：2014-07-15

申请号：US12214429

申请日：2008-06-19

申请人： Jung-Hoon Oh ,  Dong-Cheol Seo ,  Hyun-Sang Joo ,  Chang-Soo Lee

发明人： Jung-Hoon Oh ,  Dong-Cheol Seo ,  Hyun-Sang Joo ,  Chang-Soo Lee

IPC分类号： C07C309/17

CPC分类号： C07C309/12 ,  C07C25/18 ,  C07C43/225 ,  C07C69/712 ,  C07C309/08 ,  C07C381/12 ,  C07C2601/08 ,  C07C2601/14 ,  C07C2602/28 ,  C07C2602/42 ,  C07C2603/74 ,  C07C2603/86 ,  C07D333/46

摘要： An acid generating agent used for chemically amplified resist compositions is provided, which agent is represented by the following formula (1): wherein X represents a monocyclic or polycyclic hydrocarbon group having 3 to 30 carbon atoms, and having at least one hydrogen atom on the ring substituted by an alkyl or alkoxy group which may be unsubstituted or substituted with a group selected from an ether group, an ester group, a carbonyl group, an acetal group, an epoxy group, a nitrile group and an aldehyde group, or by a perfluoroalkyl group, a hydroxyalkyl group, or a cyano group; R6 is an alkyl group, an alkoxy group, or a heteroatom selected from the group consisting of N, S and F; m is an integer from 0 to 2; and A+ is an organic counterion.

摘要翻译： 提供了用于化学放大抗蚀剂组合物的酸产生剂，该试剂由下式（1）表示：其中X表示具有3至30个碳原子的单环或多环烃基，并且其上具有至少一个氢原子 可被未取代的或被选自醚基，酯基，羰基，缩醛基，环氧基，腈基和醛基中的基团取代的烷基或烷氧基取代的环，或由 全氟烷基，羟烷基或氰基; R6是烷基，烷氧基或选自N，S和F的杂原子; m为0〜2的整数; 而A +是一种有机的抗衡离子。

公开(公告)号：US08736593B2

公开(公告)日：2014-05-27

申请号：US12899848

申请日：2010-10-07

申请人： Chang-Soo Lee ,  Jong Jae Lee ,  Yunjae Park

发明人： Chang-Soo Lee ,  Jong Jae Lee ,  Yunjae Park

IPC分类号： G09G5/00

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2330/04

摘要： A power source circuit of a display apparatus includes a voltage divider, an operational amplifier, a first switch, a second switch, and a protector. The voltage divider generates a divided voltage between a first driving voltage and a ground voltage. The operational amplifier receives the divided voltage and outputs the divided voltage as a second driving voltage. The first switch is connected between a first supply voltage terminal to receive the first driving voltage and a common node. The second switch is connected between the common node and a second supply voltage terminal to receive the ground voltage. The protector is connected to the common node to limit a voltage output of the first supply voltage terminal in response to a voltage of the common node.

摘要翻译： 显示装置的电源电路包括分压器，运算放大器，第一开关，第二开关和保护器。 分压器在第一驱动电压和接地电压之间产生分压。 运算放大器接收分压，并输出分压为第二驱动电压。 第一开关连接在用于接收第一驱动电压的第一电源电压端子和公共节点之间。 第二开关连接在公共节点和第二电源电压端子之间以接收地电压。 保护器连接到公共节点，以响应于公共节点的电压来限制第一电源电压端子的电压输出。

公开(公告)号：US20130308370A1

公开(公告)日：2013-11-21

申请号：US13948138

申请日：2013-07-22

申请人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

发明人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC分类号： G11C13/00

CPC分类号： G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

摘要翻译： 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US08325208B2

公开(公告)日：2012-12-04

申请号：US12628635

申请日：2009-12-01

申请人： Young-Su Han ,  Jae-Hyoung Park ,  Po-Yun Park ,  Byung-Kil Jeon ,  Chang-Soo Lee ,  Bo-Ra Kim

发明人： Young-Su Han ,  Jae-Hyoung Park ,  Po-Yun Park ,  Byung-Kil Jeon ,  Chang-Soo Lee ,  Bo-Ra Kim

IPC分类号： G09G5/02

CPC分类号： G09G3/3611 ,  G09G3/3659 ,  G09G5/005 ,  G09G2300/0426 ,  G09G2320/0214 ,  G09G2320/0219 ,  G09G2320/0285 ,  G09G2370/08

摘要： A method for processing image data, the image data including a plurality of sub color data corresponding to a plurality of unit pixels in a row direction, wherein each unit pixel includes N sub color data having different colors, wherein N is a natural number greater than or equal to 2, includes; storing one sub color datum of the plurality of the sub color data corresponding to the unit pixels via dividing the plurality of the sub color data one by one into an individual sub color datum corresponding to a single pixel, and reading the stored sub color data, binding up the stored sub color data two by two, and storing two sub color data bound up with each other.

摘要翻译： 一种用于处理图像数据的方法，所述图像数据包括对应于行方向上的多个单位像素的多个子颜色数据，其中每个单位像素包括具有不同颜色的N个子颜色数据，其中N是大于 或等于2，包括; 通过将多个子颜色数据逐一分割为与单个像素相对应的单独子颜色数据，存储与单位像素相对应的多个子颜色数据的一个子颜色数据，并读取所存储的子颜色数据， 将所存储的子颜色数据二进制绑定，并存储彼此绑定的两个子颜色数据。