公开(公告)号：US20120182786A1

公开(公告)日：2012-07-19

申请号：US13349167

申请日：2012-01-12

申请人： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

发明人： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

IPC分类号： G11C11/21

CPC分类号： G11C13/004 ,  G11C8/10 ,  G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

摘要： A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.

摘要翻译： 存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性 并将所确定的极性的读取电压施加到所选存储单元。 输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

公开(公告)号：US08619458B2

公开(公告)日：2013-12-31

申请号：US13349167

申请日：2012-01-12

申请人： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

发明人： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C8/10 ,  G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

摘要： A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.

摘要翻译： 存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性 并将所确定的极性的读取电压施加到所选存储单元。 输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

公开(公告)号：US08654595B2

公开(公告)日：2014-02-18

申请号：US13604688

申请日：2012-09-06

申请人： Chan-Kyung Kim ,  Hong-Sun Hwang ,  Chul-Woo Park ,  Sang-Beom Kang ,  Hyung-Rok Oh

发明人： Chan-Kyung Kim ,  Hong-Sun Hwang ,  Chul-Woo Park ,  Sang-Beom Kang ,  Hyung-Rok Oh

IPC分类号： G11C7/02

CPC分类号： G11C5/145 ,  G11C7/12 ,  G11C11/1673

摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.

摘要翻译： 非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元 被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

公开(公告)号：US09183910B2

公开(公告)日：2015-11-10

申请号：US13907223

申请日：2013-05-31

申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

IPC分类号： G11C11/16 ,  G11C7/12

CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。

公开(公告)号：US07903448B2

公开(公告)日：2011-03-08

申请号：US11964142

申请日：2007-12-26

申请人： Hyung-Rok Oh ,  Sang-Beom Kang ,  Joon-Min Park ,  Woo-Yeong Cho

发明人： Hyung-Rok Oh ,  Sang-Beom Kang ,  Joon-Min Park ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/79

摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.

摘要翻译： 具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。 其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个 源线。 存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。 存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。 多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。 在存储单元写入操作中，将正电压施加到源极线。 通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US07391644B2

公开(公告)日：2008-06-24

申请号：US11605212

申请日：2006-11-29

申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

公开(公告)号：US07248494B2

公开(公告)日：2007-07-24

申请号：US11220294

申请日：2005-09-06

申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

公开(公告)号：US20140169069A1

公开(公告)日：2014-06-19

申请号：US14094021

申请日：2013-12-02

申请人： Hyung-Rok Oh

发明人： Hyung-Rok Oh

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/22 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0071 ,  G11C2213/79

摘要： A resistive memory device includes a memory cell array, a memory interface and a read sensing circuit. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of wordlines and a plurality of bitlines. The memory interface is configured to communicate with a memory controller. The read sensing circuit is coupled to the bitlines and includes at least one sensing node. The read sensing circuit performs a precharge operation to precharge the at least one sensing node between a first time point of receiving an active command through the memory interface and a second time point of receiving a read command through the memory interface, and senses data stored in the resistive memory cells to provide read data.

摘要翻译： 电阻式存储器件包括存储单元阵列，存储器接口和读取感测电路。 存储单元阵列包括耦合到多个字线和多个位线的多个电阻存储器单元。 存储器接口被配置为与存储器控制器通信。 读取感测电路耦合到位线并且包括至少一个感测节点。 读取感测电路执行预充电操作，以在通过存储器接口接收活动命令的第一时间点和通过存储器接口接收读取命令的第二时间点之间对至少一个感测节点进行预充电，并且感测存储在 电阻存储单元提供读数据。

公开(公告)号：US20100090213A1

公开(公告)日：2010-04-15

申请号：US12638599

申请日：2009-12-15

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

IPC分类号： H01L29/18

CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C17/165

摘要： A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

摘要翻译： 提供了一种编程一次性可编程器件的方法。 设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断保险丝。 保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。 还公开了相关的一次性可编程器件，相变存储器件和电子系统。