公开(公告)号：US10579462B2

公开(公告)日：2020-03-03

申请号：US15058129

申请日：2016-03-01

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for using an error signal to indicate a write request error and write request acceptance performing error handling operations using error signals. A memory module controller detects a write error for a write request in a memory module and asserts an error signal on a bus to a host memory controller in response to detecting the write error.

公开(公告)号：US10282323B2

公开(公告)日：2019-05-07

申请号：US16046587

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F12/0897 ,  G06F13/40 ,  G06F9/46 ,  G06F12/0804 ,  G06F11/10 ,  G06F12/0868 ,  G06F12/0802 ,  G06F13/00 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：US10282322B2

公开(公告)日：2019-05-07

申请号：US15482542

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukuman P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0897 ,  G06F9/46 ,  G06F13/40 ,  G06F12/02 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：US10199084B2

公开(公告)日：2019-02-05

申请号：US15197424

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Bill Nale

IPC: G11C11/406 ,  G11C7/10 ,  G06F12/00

Abstract: Examples may include techniques to use chip select signals for a dual in-line memory module (DIMM). In some examples, the chip select signals are used with either a first encoding scheme for clock enable (CKE) functionality or a second encoding scheme for on-die termination (ODT) functionality to enable memory devices on the DIMM to be accessed or controlled according to commands received with the chip select signals.

公开(公告)号：US10198306B2

公开(公告)日：2019-02-05

申请号：US14967230

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module in a first clock cycle. A chip select signal is placed on the bus for the memory module for the first half of the command. A second half of the command is placed on the bus in a second clock cycle following the first clock cycle, wherein the memory module accepts the second half of the command a delay interval from accepting the first half of the command.

公开(公告)号：US10185618B2

公开(公告)日：2019-01-22

申请号：US15011375

申请日：2016-01-29

Applicant: INTEL CORPORATION

Inventor： Bill Nale

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface configuration having a first bus width to send data over the bus in response to an interface parameter indicating a first interface parameter. Selection is made of a second bus interface configuration having a second bus width to send data over the bus in response to the interface parameter indicating a second interface parameter, wherein the first bus width has fewer bits than the second bus width.

公开(公告)号：US10146711B2

公开(公告)日：2018-12-04

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US10061719B2

公开(公告)日：2018-08-28

申请号：US14583147

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Jeffrey C. Swanson ,  Bill Nale ,  Robert G. Blankenship ,  Jeff Willey ,  Eric L. Hendrickson

IPC: G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C5/04

CPC classification number: G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

公开(公告)号：US20170322841A1

公开(公告)日：2017-11-09

申请号：US15462185

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/08 ,  H04L1/00 ,  G06F13/00 ,  G06F11/16 ,  H04L1/18

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US09658963B2

公开(公告)日：2017-05-23

申请号：US14582121

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Yen-Cheng Liu

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0831

CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.