公开(公告)号：US09959418B2

公开(公告)日：2018-05-01

申请号：US14803956

申请日：2015-07-20

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

IPC: G06F21/64 ,  G06F21/62 ,  G06F21/60 ,  G06F21/78

CPC classification number: G06F21/62 ,  G06F21/602 ,  G06F21/64 ,  G06F21/78 ,  G06F2221/2113

Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

公开(公告)号：US09910728B2

公开(公告)日：2018-03-06

申请号：US14757905

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/00 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US20180060259A1

公开(公告)日：2018-03-01

申请号：US15669197

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：US20180018267A1

公开(公告)日：2018-01-18

申请号：US15602996

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Yen-Cheng Liu

IPC: G06F12/0862 ,  G06F12/0831

CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026 ,  Y02D10/13

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

公开(公告)号：US20170249991A1

公开(公告)日：2017-08-31

申请号：US15055153

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Woojong Han ,  Mohamed Arafa ,  Brian S. Morris ,  Mani Prakash ,  James K. Pickett ,  John K. Grooms ,  Bruce Querbach ,  Edward L Payton ,  Dong Wang

IPC: G11C14/00 ,  G11C5/14 ,  G11C5/02

CPC classification number: G11C14/0009 ,  G11C5/02 ,  G11C5/025 ,  G11C5/141 ,  G11C11/005

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

公开(公告)号：US09740646B2

公开(公告)日：2017-08-22

申请号：US14578407

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：US20170103795A1

公开(公告)日：2017-04-13

申请号：US15269657

申请日：2016-09-19

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

IPC: G11C11/406 ,  G11C14/00 ,  G11C29/02 ,  G11C7/10

CPC classification number: G11C7/02 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

公开(公告)号：US20160179679A1

公开(公告)日：2016-06-23

申请号：US14582121

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Yen-Cheng Liu

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

Abstract translation: 通过用于与特定地址相关联的数据的缓冲存储器访问链路从主机设备接收推测读请求。 发送读取请求以将数据发送到存储器设备。 响应于读取请求从存储器装置接收数据，并且接收到的数据作为对在推测性读取请求之后接收的请求读取请求的响应被发送到主机设备。