公开(公告)号：US20230378061A1

公开(公告)日：2023-11-23

申请号：US18137405

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H03K19/17704 ,  H01L23/498

CPC classification number: H01L23/528 ,  H03K19/17704 ,  H01L23/49816

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US20230306173A1

公开(公告)日：2023-09-28

申请号：US18327045

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

CPC classification number: G06F30/34 ,  H03K19/17744 ,  H04L12/43 ,  G06F15/7825 ,  H03K19/17796

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US11726932B2

公开(公告)日：2023-08-15

申请号：US17347324

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： George Chong Hean Ooi ,  Lai Guan Tang ,  Chee Hak Teh

IPC: G06F13/20 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H04L49/90 ,  G06F30/34 ,  G06F115/08

CPC classification number: G06F13/20 ,  G06F30/34 ,  H01L23/538 ,  H01L24/16 ,  H01L25/18 ,  H04L49/90 ,  G06F2115/08 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

公开(公告)号：US11669472B2

公开(公告)日：2023-06-06

申请号：US17543433

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Chee Hak Teh ,  Md Altaf Hossain

IPC: G06F13/20 ,  G06F13/40

CPC classification number: G06F13/20 ,  G06F13/4027

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

公开(公告)号：US20230135934A1

公开(公告)日：2023-05-04

申请号：US18089237

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/40 ,  G06F13/16

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

公开(公告)号：US11449247B2

公开(公告)日：2022-09-20

申请号：US16953138

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Curtis Wortman ,  Jeffrey Erik Schulz

IPC: G06F3/06 ,  G06F13/38 ,  G11C7/10

Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.

公开(公告)号：US11080449B2

公开(公告)日：2021-08-03

申请号：US16833122

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US11036660B2

公开(公告)日：2021-06-15

申请号：US16368688

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： George Chong Hean Ooi ,  Lai Guan Tang ,  Chee Hak Teh

IPC: G06F13/20 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H04L12/861 ,  G06F30/34 ,  G06F115/08

Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

公开(公告)号：US10665548B2

公开(公告)日：2020-05-26

申请号：US16133216

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Chee Hak Teh

IPC: H01L23/52 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18 ,  H01L23/498

Abstract: An integrated circuit device or devices is presented that include internal connection ports to transmit data to or receive data from a first portion of the integrated circuit device. The integrated circuit device(s) also include external connection ports to transmit data to or receive data from outside the integrated circuit device, such as between integrated circuit devices. The integrated circuit device also includes remapping circuitry that remaps from a first connection between a first internal connection port of the internal connection ports and a first external connection port of the external connection ports to a second connection between a second internal connection port of the internal connection ports and a second external connection port of the external connection ports.

公开(公告)号：US20190138493A1

公开(公告)日：2019-05-09

申请号：US16235608

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.