公开(公告)号：US20150206948A1

公开(公告)日：2015-07-23

申请号：US14673163

申请日：2015-03-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC: H01L29/45 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

Abstract translation: 一种装置包括具有金属栅极和漏极阱的第一器件，其经受在漏极阱和栅极之下的沟道之间的接点处的漏极接触电压从10V降低至4-6V的串联电阻。 该装置包括设置在排水井上方和排水井上的层间电介质层（ILD0）和排水井中的自对准硅排放接头。 该设备还包括位于与低于第一设备的电压工作的第一设备不同的区域中的后续设备。

公开(公告)号：US11967615B2

公开(公告)日：2024-04-23

申请号：US15773536

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/161 ,  H01L29/165

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

公开(公告)号：US11695008B2

公开(公告)日：2023-07-04

申请号：US16846896

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Curtis Tsai ,  Chia-Hong Jan ,  Jeng-Ya David Yeh ,  Joodong Park ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/0922 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/408 ,  H01L29/40114 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7831 ,  H01L29/7851

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US11688792B2

公开(公告)日：2023-06-27

申请号：US17526986

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/762 ,  H01L21/76895 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11335601B2

公开(公告)日：2022-05-17

申请号：US17112959

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US11264329B2

公开(公告)日：2022-03-01

申请号：US16074142

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US11205708B2

公开(公告)日：2021-12-21

申请号：US15943556

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11121040B2

公开(公告)日：2021-09-14

申请号：US16317265

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Everett S. Cassidy-Comfort ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan ,  Rahul Ramaswamy ,  Neville L. Dias ,  Hsu-Yu Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

公开(公告)号：US11075286B2

公开(公告)日：2021-07-27

申请号：US16344003

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L29/10

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：US10964690B2

公开(公告)日：2021-03-30

申请号：US16474896

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Neville L. Dias ,  Rahul Ramaswamy ,  Nidhi Nidhi ,  Chen-Guan Lee

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L49/02

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.