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公开(公告)号:US10749104B2
公开(公告)日:2020-08-18
申请号:US16217807
申请日:2018-12-12
Applicant: Intel Corporation
Inventor: Huichu Liu , Daniel Morris , Tanay Karnik , Sasikanth Manipatruni , Kaushik Vaidyanathan , Ian Young
Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.
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公开(公告)号:US20200227104A1
公开(公告)日:2020-07-16
申请号:US16246358
申请日:2019-01-11
Applicant: Intel Corporation
Inventor: Tofizur Rahman , James Pellegren , Angeline Smith , Christopher Wiegand , Noriyuki Sato , Tanay Gosavi , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Benjamin Buford , Ian Young
Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
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公开(公告)号:US20200162024A1
公开(公告)日:2020-05-21
申请号:US16192841
申请日:2018-11-16
Applicant: Intel Corporation
Inventor: Dmitri E. Nikonov , Raseong Kim , Sasikanth Manipatruni , Ian A. Young , Gary Alfred Allen , Tanay Gosavi
Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.
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公开(公告)号:US20200160145A1
公开(公告)日:2020-05-21
申请号:US16194792
申请日:2018-11-19
Applicant: Intel Corporation
Inventor: Dmitri E. Nikonov , Sasikanth Manipatruni , Ian A. Young
Abstract: Embodiments may relate to a system to be used in an oscillating neural network (ONN). The system may include a control node and a plurality of nodes wirelessly communicatively coupled with a control node. A node of the plurality of nodes may be configured to identify an oscillation frequency of the node based on a weight W and an input X. The node may further be configured to transmit a wireless signal to the control node, wherein a frequency of the wireless signal oscillates based on the identified oscillation frequency. Other embodiments may be described or claimed.
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公开(公告)号:US10608167B2
公开(公告)日:2020-03-31
申请号:US15751102
申请日:2015-09-10
Applicant: Intel Corporation
Inventor: Dmitri E. Nikonov , Sasikanth Manipatruni , Anurag Chaudhry , Ian A. Young
Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.
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公开(公告)号:US20200083286A1
公开(公告)日:2020-03-12
申请号:US16128422
申请日:2018-09-11
Applicant: Intel Corporation
Inventor: Sasikanth Manipatruni , Christopher Wiegand , Tanay Gosavi , Ian Young
Abstract: An apparatus is provided which comprises: a magnetic junction (e.g., a magnetic tunneling junction or spin valve). The apparatus further includes a structure (e.g., an interconnect) comprising spin orbit material, the structure adjacent to the magnetic junction; first and second transistors. The first transistor is coupled to a bit-line and a first word-line, wherein the first transistor is adjacent to the magnetic junction. The second transistor is coupled to a first select-line and a second word-line, wherein the second transistor is adjacent to the structure, wherein the interconnect is coupled to a second select-line, and wherein the magnetic junction is between the first and second transistors.
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公开(公告)号:US20200074268A1
公开(公告)日:2020-03-05
申请号:US16121756
申请日:2018-09-05
Applicant: INTEL CORPORATION
Inventor: Dmitri Nikonov , Sasikanth Manipatruni , Ian Young
Abstract: Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.
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公开(公告)号:US10565138B2
公开(公告)日:2020-02-18
申请号:US16146534
申请日:2018-09-28
Applicant: Intel Corporation
Inventor: Jack Kavalieros , Ram Krishnamurthy , Sasikanth Manipatruni , Gregory Chen , Van Le , Amrita Mathuriya , Abhishek Sharma , Raghavan Kumar , Phil Knag , Huseyin Sumbul , Ian Young
IPC: G11C8/00 , G06F13/16 , H01L25/18 , H03K19/21 , G11C11/408 , H01L23/522 , G11C11/419
Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
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公开(公告)号:US20190386662A1
公开(公告)日:2019-12-19
申请号:US16009110
申请日:2018-06-14
Applicant: Intel Corporation
Inventor: Chia-Ching Lin , Sasikanth Manipatruni , Dmitri Nikonov , Ian A. Young , Benjamin Buford , Tanay Gosavi , Kaan Oguz , John J. Plombon
IPC: H03K19/18 , H01L43/06 , H03K19/0944 , H01F10/32 , H01F41/30
Abstract: An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.
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公开(公告)号:US20190386208A1
公开(公告)日:2019-12-19
申请号:US16009035
申请日:2018-06-14
Applicant: Intel Corporation
Inventor: Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.
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