公开(公告)号：US12048165B2

公开(公告)日：2024-07-23

申请号：US16914140

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H10B53/00 ,  G11C11/22 ,  H01G4/008 ,  H01L27/08 ,  H01L49/02 ,  H10B53/10

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01G4/008 ,  H01L27/0805 ,  H01L28/65 ,  H10B53/10

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US20240114695A1

公开(公告)日：2024-04-04

申请号：US17957560

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Christopher Neumann ,  Shriram Shivaraman ,  Brian Doyle ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. A capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. The cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.

公开(公告)号：US20240114693A1

公开(公告)日：2024-04-04

申请号：US17958202

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher M. Neumann ,  Brian Doyle ,  Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Uygar E. Avci ,  Eungnak Han ,  Manish Chandhok ,  Nafees Aminul Kabir ,  Gurpreet Singh

IPC: H01L27/11514 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11504

CPC classification number: H01L27/11514 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11504

Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.

公开(公告)号：US20240113123A1

公开(公告)日：2024-04-04

申请号：US17957836

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Sou-Chi Chang

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11838

Abstract: An apparatus is provided which comprises: a plurality of logic blocks comprising transistors on a substrate, the logic blocks to implement logic functions; a plurality of input/output (I/O) blocks connecting the logic blocks with components external to the apparatus; a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the substrate, the wires and vias conductively coupling the plurality of logic blocks and the plurality of I/O blocks; a plurality of programmable switches to configure connections between the plurality of logic blocks and the plurality of I/O blocks; and a ferroelectric material in a capacitor coupled to the gate or on the gate dielectric itself of one or more of the transistors. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240112731A1

公开(公告)日：2024-04-04

申请号：US17957957

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Saima Siddiqui ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Techniques and mechanisms for operating a ferroelectric (FE) circuit element as a cell of a crossbar memory array. In an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. The data storage cell is a FE circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. One such layer comprises a FE nitride or a FE oxide. The FE circuit element is operable to selectively enable, or disable, operation as a diode. In another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the FE circuit element to a particular data bit value.

公开(公告)号：US20220199758A1

公开(公告)日：2022-06-23

申请号：US17132970

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Jason C. Retasket ,  Matthew V. Metz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Kaan Oguz ,  Uygar E. Avci ,  Edward Johnson

IPC: H01L49/02 ,  H01L29/51 ,  H01L23/522 ,  H01L27/06 ,  H01L29/78

Abstract: Capacitors with a carbon-based electrode layer in contact with a ferroelectric insulator. The insulator may be a perovskite oxide. Low reactivity of the carbon-based electrode may improve stability of a ferroelectric capacitor. A carbon-based electrode layer may be predominantly carbon and have a low electrical resistivity. A carbon-based electrode layer may be the only layer of an electrode, or it may be a barrier between the insulator and another electrode layer. Both electrodes of a capacitor may include a carbon-based electrode layer, or a carbon-based electrode layer may be included in only one electrode.

公开(公告)号：US20210398993A1

公开(公告)日：2021-12-23

申请号：US16906217

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC: H01L27/11507 ,  H01L23/522 ,  H01L21/768

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

公开(公告)号：US20200286984A1

公开(公告)日：2020-09-10

申请号：US16296035

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/11507

Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.

公开(公告)号：US20200286685A1

公开(公告)日：2020-09-10

申请号：US16294811

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.