公开(公告)号：US20220199760A1

公开(公告)日：2022-06-23

申请号：US17129875

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Noriyuki SATO ,  Sudarat LEE ,  Scott B. CLENDENNING ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Hui Jae YOO ,  Van H. LE

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01G4/10

Abstract: An integrated circuit (IC) structure having a plurality of backend double-walled capacitors (DWCs) are described. In an example, a first interconnect layer is disposed over a substrate and a second interconnect layer is disposed over the first interconnect layer. In the example, a plurality of DWCs are disposed in the first interconnect layer or the second interconnect layer to provide capacitance to assist the first interconnect layer and the second interconnect layer in providing electrical signal routing and power distribution to one or more devices in the IC structure. In examples, the IC structure includes a logic IC or a coupling substrate.

公开(公告)号：US20220199609A1

公开(公告)日：2022-06-23

申请号：US17133595

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Urusa ALAAN ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Benjamin ORR ,  Nicholas THOMSON ,  Ayan KAR ,  Arnab SEN GUPTA ,  Kaan OGUZ ,  Brian S. DOYLE ,  Prashant MAJHI ,  Van H. LE ,  Elijah V. KARPOV

IPC: H01L27/02 ,  H02H9/04

Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

公开(公告)号：US20210305255A1

公开(公告)日：2021-09-30

申请号：US16828507

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Juan G. ALZATE VINASCO ,  Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Kimberly L. PIERCE ,  Elliot N. TAN ,  Yu-Jin CHEN ,  Van H. LE ,  Pei-Hua WANG ,  Bernhard SELL

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20210288049A1

公开(公告)日：2021-09-16

申请号：US17334425

申请日：2021-05-28

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Jack T. KAVALIEROS

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

公开(公告)号：US20200335635A1

公开(公告)日：2020-10-22

申请号：US16957617

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/786 ,  H01L29/423

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US20200287006A1

公开(公告)日：2020-09-10

申请号：US16645405

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Li Huey TAN ,  Tristan TRONIC ,  Benjamin CHU-KUNG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a gate electrode above a substrate and a channel layer above the gate electrode. A source electrode may be above the channel layer and adjacent to a source area of the channel layer, and a drain electrode may be above the channel layer and adjacent to a drain area of the channel layer. A passivation layer may be above the channel layer and between the source electrode and the drain electrode, and a top dielectric layer may be above the gate electrode, the channel layer, the source electrode, the drain electrode, and the passivation layer. In addition, an air gap may be above the passivation layer and below the top dielectric layer, and between the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098874A1

公开(公告)日：2020-03-26

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin WEBER ,  Harold KENNEL ,  Abhishek SHARMA ,  Christopher JEZEWSKI ,  Matthew V. METZ ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Van H. LE ,  Arnab SEN GUPTA

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L29/267 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L21/322

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098754A1

公开(公告)日：2020-03-26

申请号：US16606702

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Jack T. KAVALIEROS

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

公开(公告)号：US20200066326A1

公开(公告)日：2020-02-27

申请号：US15776058

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Gilbert DEWEY ,  Van H. LE ,  Jack KAVALIEROS ,  Mesut METERELLIYOZ

IPC: G11C11/4097 ,  G11C11/405 ,  H01L27/108

Abstract: A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

公开(公告)号：US20190305136A1

公开(公告)日：2019-10-03

申请号：US15943584

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sean MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Van H. LE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L27/12

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.