公开(公告)号：US20230178437A1

公开(公告)日：2023-06-08

申请号：US17545013

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Balasubramanian S. Pranatharthiharan ,  Stuart Sieg ,  Nelson Felix ,  Veeraraghavan S. Basker

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/66545 ,  H01L29/786 ,  H01L27/088 ,  H01L21/823437

Abstract: Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form transistors on a substrate. The fabrication operations include forming a sacrificial metal gate and forming a shared non-sacrificial metal gate. The sacrificial metal gate is recessed to form a sacrificial metal gate, and the shared non-sacrificial metal gate is recessed to form a recessed shared non-sacrificial metal gate. A pattern is formed over the sacrificial metal gate and the recessed shared non-sacrificial metal gate. The pattern defines a single diffusion break footprint over a top surface of the sacrificial metal gate, along with a gate-cut footprint over a central region of a top surface of the recessed shared non-sacrificial metal gate.

公开(公告)号：US20230096938A1

公开(公告)日：2023-03-30

申请号：US17481981

申请日：2021-09-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Ashim Dutta ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: H01L21/033 ,  H01L21/311

Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

公开(公告)号：US11500293B2

公开(公告)日：2022-11-15

申请号：US16657654

申请日：2019-10-18

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Indira Seshadri ,  Jing Guo ,  Ashim Dutta ,  Nelson Felix

IPC: G03F7/20 ,  H01L21/308 ,  H01L21/027 ,  G03F1/22 ,  H01L21/033 ,  G03F1/54 ,  G03F7/40

Abstract: A semiconductor structure comprises a semiconductor substrate, and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack comprises at least a hard mask layer and a resist layer formed over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on a developed pattern of the resist layer through inclusion in the hard mask layer of one or more materials inhibiting deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer. The hard mask layer illustratively comprises, for example, at least one of a grafted self-assembled monolayer configured to inhibit deposition of the metal-containing layer, and a grafted polymer brush material configured to inhibit deposition of the metal-containing layer.

公开(公告)号：US11300881B2

公开(公告)日：2022-04-12

申请号：US16167996

申请日：2018-10-23

Applicant: International Business Machines Corporation

Inventor： Luciana Meli Thompson ,  Jing Guo ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: G03F7/40 ,  G03F7/00 ,  G03F7/20 ,  H01L21/311 ,  H01L21/027

Abstract: A photolithography patterning stack and method for repairing defects in the stack. The stack includes an organic planarization layer, a hardmask layer, and a plurality of patterned photoresist lines in contact with the hardmask layer. A plurality of trenches is situated between the plurality of patterned photoresist lines. Each trench exposes a portion of the hardmask layer. A repairing layer is formed in contact with and only bonded to surfaces of the plurality of patterned photoresist lines. The method includes forming a photolithographic patterning stack. The stack includes at least a hardmask layer formed on one or more underlayers and a photoresist layer formed in contact with the hardmask layer. The photoresist layer is patterned into a plurality of patterned portions. A repairing layer is formed in contact with and only bonded to surfaces of each patterned portion of the plurality of portions.

公开(公告)号：US11199778B2

公开(公告)日：2021-12-14

申请号：US16299645

申请日：2019-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jing Guo ,  Bharat Kumar ,  Ekmini A. De Silva ,  Jennifer Church ,  Dario Goldfarb ,  Nelson Felix

IPC: G03F7/20 ,  G03F7/32

Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

公开(公告)号：US11133195B2

公开(公告)日：2021-09-28

申请号：US16400003

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

IPC: H01L21/308 ,  H01L21/033

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

公开(公告)号：US11121024B2

公开(公告)日：2021-09-14

申请号：US16542502

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Nelson Felix ,  Indira Seshadri ,  Stuart A. Sieg

IPC: H01L21/762 ,  H01L23/544 ,  H01L21/027 ,  H01L21/768 ,  H01L21/48 ,  B82Y40/00

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

公开(公告)号：US11084032B2

公开(公告)日：2021-08-10

申请号：US16419707

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Joshua T. Smith ,  Bassem M. Hamieh ,  Nelson Felix ,  Robert L. Bruce

IPC: B01L3/00 ,  B81C1/00

Abstract: A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

公开(公告)号：US20210143013A1

公开(公告)日：2021-05-13

申请号：US16682494

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  Nelson Felix ,  Yann Mignot ,  Ekmini Anuja De Silva ,  John Arnold ,  Allen Gabor

IPC: H01L21/033 ,  H01L21/321 ,  H01L21/768

Abstract: A method for fabricating a semiconductor device includes forming a plurality of mandrel cuts from a first set of mandrels of a base structure using lithography, surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, forming a flowable material layer on exposed surfaces of the mandrel-spacer structures, and performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

公开(公告)号：US10950440B2

公开(公告)日：2021-03-16

申请号：US16691645

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Abraham Arceo de la Pena ,  Ekmini Anuja De Silva ,  Nelson Felix

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/3215 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.