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公开(公告)号：US20190252499A1
公开(公告)日：2019-08-15
申请号：US16395024
申请日：2019-04-25
Applicant: International Business Machines Corporation
Inventor： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC: H01L29/12 , H01L23/52 , H01L29/06 , H01L27/085
Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
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公开(公告)号：US20190131383A1
公开(公告)日：2019-05-02
申请号：US15797848
申请日：2017-10-30
Applicant: International Business Machines Corporation
Inventor： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC: H01L49/02 , H01L27/11507 , H01B3/10 , H01L21/02 , H01L21/283 , H01L21/3213
CPC classification number: H01L28/40 , H01B3/10 , H01L21/02181 , H01L21/02356 , H01L21/283 , H01L21/32133 , H01L27/11507 , H01L28/55 , H01L28/60
Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
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公开(公告)号：US20180323188A1
公开(公告)日：2018-11-08
申请号：US15585876
申请日：2017-05-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
CPC classification number: H01L27/0629 , H01L21/28291 , H01L27/11507 , H01L27/1159
Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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公开(公告)号：US09934838B1
公开(公告)日：2018-04-03
申请号：US15591834
申请日：2017-05-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Jin-Ping Han , Xiao Sun , Teng Yang
CPC classification number: G11C11/2273 , G06N3/04 , G06N3/084 , G11C11/223 , G11C11/2259 , G11C11/2275 , G11C11/2277 , G11C11/54 , G11C11/56 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0073 , G11C2013/0092 , G11C2213/53
Abstract: A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.
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