公开(公告)号：US08222673B2

公开(公告)日：2012-07-17

申请号：US12795683

申请日：2010-06-08

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08124515B2

公开(公告)日：2012-02-28

申请号：US12469418

申请日：2009-05-20

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3215

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度，形成包括金属栅电极的改进的半导体器件，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US08076209B2

公开(公告)日：2011-12-13

申请号：US12771948

申请日：2010-04-30

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/7847 ,  H01L29/66636

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract translation: 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，使用栅电极作为蚀刻掩模将凹陷蚀刻到衬底中，沉积应力诱导 覆盖栅极电极，退火含硅衬底以使栅电极重结晶，去除应力诱导层，以及在凹槽中外延生长杂质掺杂的含硅区域。

公开(公告)号：US08026539B2

公开(公告)日：2011-09-27

申请号：US12388094

申请日：2009-02-18

Applicant: Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

Inventor： Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

IPC: H01L29/76

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.

Abstract translation: 提供了用于形成包括半导体衬底的半导体器件的方法。 根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层 含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

公开(公告)号：US20100295103A1

公开(公告)日：2010-11-25

申请号：US12469418

申请日：2009-05-20

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度，形成包括金属栅电极的改进的半导体器件，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US20100289089A1

公开(公告)日：2010-11-18

申请号：US12775555

申请日：2010-05-07

Applicant: Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

Inventor： Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/20 ,  H01L21/336

CPC classification number: H01L21/823462 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies.

Abstract translation: 复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。 以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。

公开(公告)号：US20100207176A1

公开(公告)日：2010-08-19

申请号：US12388094

申请日：2009-02-18

Applicant: Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

Inventor： Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

IPC: H01L29/78 ,  H01L21/4763

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.

Abstract translation: 提供了用于形成包括半导体衬底的半导体器件的方法。 根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层 含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

公开(公告)号：US07632727B2

公开(公告)日：2009-12-15

申请号：US12119384

申请日：2008-05-12

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

IPC: H01L29/772

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract translation: 提供一种制造半导体晶体管器件的方法。 制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。 然后，围绕栅极结构的侧壁形成间隔物。 接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。 在该步骤中，栅极结构和间隔物用作离子注入掩模。 离子在半导体材料中形成非晶化区域。 此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。 此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

公开(公告)号：US20080248598A1

公开(公告)日：2008-10-09

申请号：US11697955

申请日：2007-04-09

Applicant: Rohit Pal ,  Alok Vaid

Inventor： Rohit Pal ,  Alok Vaid

IPC: H01L21/66 ,  H01L21/306 ,  H01L23/58

CPC classification number: H01L22/12

Abstract: A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.

Abstract translation: 一种方法包括照亮包括至少部分地形成在半导体材料中的第一多个应力材料区域的第一栅格的至少一部分。 测量从第一格栅的照明部分反射的光以产生第一反射曲线。 基于第一反射曲线确定第一多个应力材料区域的特性。 测试结构包括相对于半导体层的表面凹陷并限定第一格栅的第一多个应力材料区域。 半导体层的第一多个暴露部分设置在第一多个应力材料区域中的每一个之间。

公开(公告)号：US08525289B2

公开(公告)日：2013-09-03

申请号：US13444955

申请日：2012-04-12

Applicant: Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

Inventor： Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

IPC: H01L23/58

CPC classification number: H01L21/823462 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract translation: 复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。 以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。 此外，可以为两种类型的晶体管沉积单个含金属的电极材料。