公开(公告)号：US20210407907A1

公开(公告)日：2021-12-30

申请号：US16911879

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/32 ,  H01L21/768

Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.

公开(公告)号：US10892184B2

公开(公告)日：2021-01-12

申请号：US16317015

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Kevin L. Lin ,  James M. Blackwell ,  Rami Hourani ,  Eungnak Han

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

公开(公告)号：US20200350246A1

公开(公告)日：2020-11-05

申请号：US16642851

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Richard Farrington Vreeland ,  Sansaptak Dasgupta

IPC: H01L23/522 ,  H01L23/532

Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

公开(公告)号：US10796909B2

公开(公告)日：2020-10-06

申请号：US16343385

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Kevin L. Lin ,  James M. Blackwell

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

公开(公告)号：US20200219804A1

公开(公告)日：2020-07-09

申请号：US16243790

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ashish Agrawal ,  Kevin L. Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/24 ,  H01L29/423 ,  H01L23/535 ,  H01L29/786 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/4763

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

公开(公告)号：US10508961B2

公开(公告)日：2019-12-17

申请号：US14951422

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC: G01L9/00 ,  B81B7/00 ,  B81C1/00 ,  H01L23/00 ,  H01L29/84

Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity.

公开(公告)号：US09489928B2

公开(公告)日：2016-11-08

申请号：US14139536

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Nathan R. Andrysco ,  Kevin L. Lin

IPC: G09G5/391 ,  G06F3/00

CPC classification number: G09G5/391 ,  G06F3/005 ,  G09G2320/0261 ,  G09G2340/0407

Abstract: Techniques are disclosed for improving energy efficiency of displays, and in particular, displays capable of selective refresh. In an embodiment, the techniques include adjusting the effective resolution of a display based on the viewer's distance from the display. The effective resolution adjustment can be accomplished by, for example, grouping individual pixels or blurring the display buffer (or both pixel grouping and blurring) based on the viewer's distance from the display. Such an adjustment has the effect of creating enlarged pixels from a plurality of smaller pixels. In any such cases, each of the enlarged pixels (also called macro-pixels) can then be selectively refreshed based on changes from the previous frame. In addition, even if one of the macro-pixels has changed from the last frame, it also need not be refreshed if the viewer would not perceive that change given a subtle or otherwise unperceivable difference in intensity.

Abstract translation: 公开了用于提高显示器的能量效率的技术，特别是能够进行选择性刷新的显示器。 在一个实施例中，这些技术包括基于观看者与显示器的距离来调整显示器的有效分辨率。 可以通过例如基于观看者与显示器的距离来分组单个像素或模糊显示缓冲器（或者像素分组和模糊两者）来实现有效分辨率调整。 这种调整具有从多个较小像素产生放大像素的效果。 在任何这种情况下，可以基于来自先前帧的改变来选择性地刷新每个放大像素（也称为宏像素）。 另外，即使其中一个宏像素从最后一帧改变，如果观察者不会感觉到这种变化给出了微妙或其他不可察觉的强度差异，那么它也不需要刷新。

公开(公告)号：US09324652B2

公开(公告)日：2016-04-26

申请号：US14630572

申请日：2015-02-24

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Yan A. Borodovsky ,  Florian Gstrein ,  David N. Shykind ,  Kevin L. Lin

IPC: H01L21/336 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L21/3213 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Abstract translation: 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。