公开(公告)号：US20240178157A1

公开(公告)日：2024-05-30

申请号：US18071257

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Whitney BRYKS ,  Brandon C. MARIN ,  Vishal Bhimrao ZADE ,  Deniz TURAN ,  Srinivas V. PIETAMBARAM

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822

Abstract: Embodiments disclosed herein include package substrates. In a particular embodiment, the package substrate comprises a core. The core may be a glass core. In an embodiment, buildup layers are provided over the core, and a shape memory polymer (SMP) is provided over the core.

公开(公告)号：US20240111092A1

公开(公告)日：2024-04-04

申请号：US17956757

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13

Abstract: Embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a PIC. In embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the PIC and the optical waveguide. In embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the PIC interacts with in a Plasmon effect to focus the light on to the optical waveguide. Other embodiments may be described and/or claimed.

公开(公告)号：US20230100576A1

公开(公告)日：2023-03-30

申请号：US17478450

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Jianyong XIE ,  Krishna Vasanth VALAVALA

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.

公开(公告)号：US20230097236A1

公开(公告)日：2023-03-30

申请号：US17485287

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Aleksandar ALEKSOV ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Telesphor KAMGAING ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises: a core substrate. In an embodiment, the core substrate comprises glass. In an embodiment, a via passes through the core substrate. In an embodiment, a die is coupled to the package substrate, where the die comprises an IO interface. In an embodiment, the IO interface is electrically coupled to the via and the via is within a footprint of the die.

公开(公告)号：US20230092242A1

公开(公告)日：2023-03-23

申请号：US17507010

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Gang DUAN

IPC: H01L23/15 ,  H01L21/768

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20230091666A1

公开(公告)日：2023-03-23

申请号：US17482399

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Aleksandar ALEKSOV ,  Helme A. CASTRO DE LA TORRE ,  Kristof DARMAWIKARTA ,  Darko GRUJICIC ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Rengarajan SHANMUGAM ,  Thomas L. SOUNART ,  Marcel WALL

IPC: H05K1/18 ,  H05K1/03 ,  H01G4/33 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20230091050A1

公开(公告)日：2023-03-23

申请号：US17479031

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Pooya TADAYON ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Changhua LIU ,  Kemal AYGÜN

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to optical interconnects and optical waveguides within a glass layer of a semiconductor package, where dies that are physically and optically coupled with the glass layer are optically coupled with each other via the optical waveguides. One or more reflectors may be used to direct the optical pathway through the glass layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230088392A1

公开(公告)日：2023-03-23

申请号：US17481258

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Rahul N. MANEPALLI ,  Ravindra TANIKELLA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.

公开(公告)号：US20230087838A1

公开(公告)日：2023-03-23

申请号：US17479033

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Rahul N. MANEPALLI ,  Srinivas V. PIETAMBARAM ,  Ravindra TANIKELLA ,  Sameer PAITAL ,  Gang DUAN

IPC: H01L23/29 ,  C03C17/32

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.

公开(公告)号：US20230079607A1

公开(公告)日：2023-03-16

申请号：US17473099

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Leonel ARANA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L21/48 ,  H01L21/683

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.