公开(公告)号：US20100269079A1

公开(公告)日：2010-10-21

申请号：US12426475

申请日：2009-04-20

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07805693B2

公开(公告)日：2010-09-28

申请号：US12031734

申请日：2008-02-15

Applicant: Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Abstract translation: 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。

公开(公告)号：US20090278222A1

公开(公告)日：2009-11-12

申请号：US12117771

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC: H01L27/00 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072

Abstract: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

Abstract translation: 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

公开(公告)号：US20090222783A1

公开(公告)日：2009-09-03

申请号：US12039109

申请日：2008-02-28

Applicant: James A. Culp ,  Gregory A. Northrop ,  Ming Yin

Inventor： James A. Culp ,  Gregory A. Northrop ,  Ming Yin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract translation: 因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。 特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。 外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。 每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。 内部电池或内部视图包括形成电池组件的规则形状，并定义电池构造细节，并通过构造进行接地规则清洁，或通过仿真或硬件验证。

公开(公告)号：US20080279443A1

公开(公告)日：2008-11-13

申请号：US12182409

申请日：2008-07-30

Applicant: Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

Inventor： Karen D. Badger ,  James A. Culp ,  Azalia A. Krasnoperova

IPC: G06K9/74

CPC classification number: G03F7/70441

Abstract: A mask inspection method and system. Provided is a mask fabrication database describing geometrical shapes S to be printed as part of a mask pattern on a reticle to fabricate a mask through use of a mask fabrication tooling. The shapes S appear on the mask as shapes S′ upon being printed. At least one of the shapes S′ may be geometrically distorted relative to a corresponding at least one of the shapes S due to a lack of precision in the mask fabrication tooling. Also provided is a mask inspection database to be used for inspecting the mask after the mask has been fabricated by the mask fabrication tooling. The mask inspection database describes shapes S″ approximating the shapes S′. A geometric distortion between the shapes S′ and S″ is less than a corresponding geometric distortion between the shapes S′ and S.

Abstract translation: 面罩检查方法和系统。 提供了一种掩模制造数据库，其描述要在掩模版上作为掩模图案的一部分打印的几何形状S，以通过使用掩模制造工具来制造掩模。 形状S在印刷时作为形状S'出现在掩模上。 由于在掩模制造工具中缺乏精度，至少一种形状S'可能相对于形状S中的相应的至少一个形状几何失真。 还提供了掩模检查数据库，用于在通过掩模制造工具制造掩模之后检查掩模。 掩模检查数据库描述形状S'近似形状S'。 形状S'和S“之间的几何变形小于形状S'和S之间的对应的几何变形。

公开(公告)号：US08458625B2

公开(公告)日：2013-06-04

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US20130031519A1

公开(公告)日：2013-01-31

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US08232215B2

公开(公告)日：2012-07-31

申请号：US12622557

申请日：2009-11-20

Applicant: James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L21/302

CPC classification number: H01L21/31144

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract translation: 用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。 保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。 用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻 的部分蚀刻的间隔材料层。 用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

公开(公告)号：US20120149200A1

公开(公告)日：2012-06-14

申请号：US12966432

申请日：2010-12-13

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/28035 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/78

Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Abstract translation: 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。