公开(公告)号：US07123521B1

公开(公告)日：2006-10-17

申请号：US11115489

申请日：2005-04-27

Applicant: Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

Inventor： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

IPC: G11C7/10

CPC classification number: G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract translation: 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。

公开(公告)号：US06778435B1

公开(公告)日：2004-08-17

申请号：US10170816

申请日：2002-06-12

Applicant: Jin-Man Han ,  Farid Nemati ,  Seong-Ook Jeong

Inventor： Jin-Man Han ,  Farid Nemati ,  Seong-Ook Jeong

IPC: G11C1134

CPC classification number: G11C11/39 ,  G11C7/18 ,  G11C8/08

Abstract: A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical “0” and “1.” An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.

Abstract translation: 一种存储器架构，特别适用于提供一种架构来容纳一个或多个基于TCCT的存储器单元并提供参考信号。 存储器架构被设计为有效地将存储的信息从存储器单元解析成逻辑值，例如逻辑“0”和“1”。 示例性存储器架构包括数据块，其包括第一组一个或多个位线，其中字线一行延伸到所述一个或多个位线的第一组的第一子集。 数据块还包括延伸到一个或多个位线的第一组的第二子集的字线两行。 存储器单元耦合到字线一行，字线两行和位线的第一和第二子集的公共位线。

公开(公告)号：US5640360A

公开(公告)日：1997-06-17

申请号：US591118

申请日：1996-01-25

Applicant: Gyu-Hong Kim ,  Jin-Man Han ,  Hyung-Dong Kim

Inventor： Gyu-Hong Kim ,  Jin-Man Han ,  Hyung-Dong Kim

IPC: G11C11/413 ,  G06F12/02 ,  G11C11/408 ,  B11C8/00

CPC classification number: G11C11/4082

Abstract: An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.

Abstract translation: 用于半导体存储器件的地址缓冲电路包括分别根据第一和第二地址输入控制信号可选择地连接到第一节点的第一和第二地址输入。 该装置还包括由刷新模式信号控制并选择性地输出第一或第二地址使能信号的第一和第二开关。 此外，提供锁存器，其将输入到第一节点的地址信号锁存，并且在所选择的第一或第二地址使能信号的周期中输出锁存的地址信号。

公开(公告)号：US08772857B2

公开(公告)日：2014-07-08

申请号：US13221380

申请日：2011-08-30

Applicant: Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

Inventor： Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

IPC: H01L29/788

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

Abstract translation: 垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。 通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

公开(公告)号：US20120275230A1

公开(公告)日：2012-11-01

申请号：US13546944

申请日：2012-07-11

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C16/3495 ,  G11C2216/14

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

Abstract translation: 公开了诸如涉及闪存装置的方法和装置。 一种这样的方法包括将存储器单元上的数据存储在包括字线上的多个字线和多个存储器单元的存储器块上。 字线包括一个或多个底边字线，一个或多个顶边字线，以及底边和顶边字线之间的中间字线。 数据首先存储在中间字线上的存储单元上。 然后，数据的剩余部分（如果有的话）被存储在底部边缘字线和/或顶部边缘字线上的存储器单元上。 该方法通过防止底部或顶部边缘字线上的存储器单元的过早故障来增强闪存的寿命，这可能更容易发生故障。

公开(公告)号：US07855927B2

公开(公告)日：2010-12-21

申请号：US12497998

申请日：2009-07-06

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C16/0483 ,  G11C16/12 ,  G11C2207/229

Abstract: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

Abstract translation: 本发明提供了方法和装置。 NAND闪存器件以第一频率接收命令和地址信号，并以大于第一频率的第二频率接收数据信号。

公开(公告)号：US07808822B2

公开(公告)日：2010-10-05

申请号：US12417224

申请日：2009-04-02

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Abstract translation: 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

公开(公告)号：US20100165741A1

公开(公告)日：2010-07-01

申请号：US12721693

申请日：2010-03-11

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/0483

Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.

Abstract translation: 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将感测电压施加到用于感测所选存储单元的所选择的接入线 该方法还包括在施加感测电压的同时向未选择的接入线施加动态通过电压。

公开(公告)号：US20100142280A1

公开(公告)日：2010-06-10

申请号：US12703901

申请日：2010-02-11

Applicant: Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

Inventor： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20100020609A1

公开(公告)日：2010-01-28

申请号：US12178192

申请日：2008-07-23

Applicant: Jin-Man Han ,  Aaron Yip

Inventor： Jin-Man Han ,  Aaron Yip

IPC: G11C16/04

CPC classification number: G11C29/846 ,  G11C29/82 ,  G11C2216/30

Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Abstract translation: 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个列的存储块。 每个列包括位线和位线上的多个存储单元。 多个列包括多组常规列和多组冗余列。 该装置还包括多个数据锁存器。 每个数据锁存器被配置为存储从相应的一组常规列读取的数据。 该装置还包括多个冗余数据锁存器。 每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。 该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。