公开(公告)号：US20060192266A1

公开(公告)日：2006-08-31

申请号：US11067983

申请日：2005-02-28

申请人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl-Heinz Kuesters

发明人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl-Heinz Kuesters

IPC分类号： H01L29/00

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。

公开(公告)号：US06940123B2

公开(公告)日：2005-09-06

申请号：US10713689

申请日：2003-11-14

申请人： Christoph Ludwig

发明人： Christoph Ludwig

IPC分类号： H01L21/8246 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  Y10S438/931

摘要： In a matrix-shaped configuration of memory transistors, word lines are disposed on a top side of a semiconductor body and are parallel to one another. Bit lines run transversely with respect thereto and are formed by polysilicon strips which are applied on the top side and are isolated from the semiconductor body by barrier layers functioning as diffusion barriers.

摘要翻译： 在存储晶体管的矩阵状配置中，字线被布置在半导体本体的顶侧并且彼此平行。 位线相对于其横向延伸，并且由施加在顶侧上的多晶硅条形成，并且通过用作扩散阻挡层的阻挡层与半导体本体隔离。

公开(公告)号：US06909153B2

公开(公告)日：2005-06-21

申请号：US10159859

申请日：2002-05-31

申请人： Christoph Ludwig ,  Klaus-Dieter Morhard ,  Christoph Kutter

发明人： Christoph Ludwig ,  Klaus-Dieter Morhard ,  Christoph Kutter

IPC分类号： H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/115 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

摘要翻译： 半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道 导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于 每个第一轨道导体303和位于其上方的相应的第三轨道导体307之间的电接触305。

公开(公告)号：US06711065B2

公开(公告)日：2004-03-23

申请号：US10109270

申请日：2002-03-28

申请人： Danny Shum ,  George Tempel ,  Christoph Ludwig

发明人： Danny Shum ,  George Tempel ,  Christoph Ludwig

IPC分类号： G11C700

CPC分类号： G11C16/3404

摘要： Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

摘要翻译： 闪存EEPROM单元被擦除并通过两步处理恢复到公共阈值电压。 首先，细胞被擦除。 第二，固定（控制）门被设置为与编程电压相同极性的电压，并且大约为编程电压的一半。 允许源浮动，漏极（位线）和体被设置在与编程电压极性相反的极低电平和极性。

公开(公告)号：US06654281B2

公开(公告)日：2003-11-25

申请号：US10177884

申请日：2002-06-20

申请人： Georg Georgakos ,  Kai Huckels ,  Jakob Kriz ,  Christoph Kutter ,  Andreas Liebelt ,  Christoph Ludwig ,  Elard Stein von Kamienski ,  Peter Wawer

发明人： Georg Georgakos ,  Kai Huckels ,  Jakob Kriz ,  Christoph Kutter ,  Andreas Liebelt ,  Christoph Ludwig ,  Elard Stein von Kamienski ,  Peter Wawer

IPC分类号： G11C1604

CPC分类号： H01L27/11519 ,  G11C16/0416 ,  H01L27/11521

摘要： A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.

公开(公告)号：USD405791S

公开(公告)日：1999-02-16

申请号：US78191

申请日：1997-10-21

申请人： Wihelm Menke ,  Boerge Heidersberger ,  Fritz Biermeier ,  Christoph Ludwig ,  Christoph Konnecke ,  William J. Ward, Jr.

设计人： Wihelm Menke ,  Boerge Heidersberger ,  Fritz Biermeier ,  Christoph Ludwig ,  Christoph Konnecke ,  William J. Ward, Jr.

公开(公告)号：US08595449B2

公开(公告)日：2013-11-26

申请号：US12202581

申请日：2008-09-02

申请人： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

发明人： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C13/00 ,  G11C11/00 ,  G11C11/34 ,  G11C16/06 ,  G11C16/04 ,  G11C7/04

CPC分类号： G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431

摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

摘要翻译： 集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。 存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。 内存调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

公开(公告)号：US07678654B2

公开(公告)日：2010-03-16

申请号：US11478313

申请日：2006-06-30

申请人： Christoph Kleint ,  Clemens Fitz ,  Ulrike Bewersdorff-Sarlette ,  Christoph Ludwig ,  David Pritchard ,  Torsten Müller ,  Hocine Boubekeur

发明人： Christoph Kleint ,  Clemens Fitz ,  Ulrike Bewersdorff-Sarlette ,  Christoph Ludwig ,  David Pritchard ,  Torsten Müller ,  Hocine Boubekeur

IPC分类号： H01L21/8247 ,  H01L29/792

CPC分类号： G11C5/063 ,  G11C7/18 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

摘要翻译： 存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。 每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

公开(公告)号：US07122434B2

公开(公告)日：2006-10-17

申请号：US11124726

申请日：2005-05-09

申请人： Christoph Ludwig ,  Klaus-Dieter Morhard ,  Christoph Kutter

发明人： Christoph Ludwig ,  Klaus-Dieter Morhard ,  Christoph Kutter

IPC分类号： H01L21/8234

CPC分类号： H01L27/115 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

摘要翻译： 半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道 导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于 每个第一轨道导体303和位于其上方的对应的第三轨道导体307之间的电接触305。

公开(公告)号：US06368970B1

公开(公告)日：2002-04-09

申请号：US09645238

申请日：2000-08-24

申请人： Ayad Abdul-Hak ,  Achim Gratz ,  Christoph Ludwig ,  Reinhold Rennekamp ,  Elard Stein Von Kamienski ,  Peter Wawer

发明人： Ayad Abdul-Hak ,  Achim Gratz ,  Christoph Ludwig ,  Reinhold Rennekamp ,  Elard Stein Von Kamienski ,  Peter Wawer

IPC分类号： H01L21302

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

摘要翻译： 一种制造半导体结构的方法包括以下步骤：提供半导体衬底，在半导体衬底上提供缓冲氧化物层，并在缓冲氧化物层上提供硬掩模。 通过使用硬掩模蚀刻STI沟槽，并且在STI沟槽中提供衬垫氧化物层。 去除硬掩模以暴露缓冲氧化物层，并通过蚀刻工艺除去缓冲氧化物层。 在蚀刻工艺中，缓冲氧化物层比衬垫氧化物层蚀刻得更快。 在半导体衬底上设置栅氧化层。 还提供半导体配置。