摘要:
A non-photlithographic, physical patterning process, which is useful for selectively etching of a substrate, is provided. The process comprises electrostatically charging liquid droplets which are selectively etchable with respect to the substrate, dispersing the droplets onto substrate in a pattern; and etching the substrate using the droplets as a mask.
摘要:
Systems and methods for use with an optical communication beam are disclosed. The system allows the beam of light to operate at an adequate power level that provides a robust optical link while minimizing any safety risk to humans. The system calibrates and controls the gain for an avalanche photodiode detector (APD). A detector circuit is used to calibrate the APD. Once calibrated, the detector circuit further provides an electrical bias to the APD to process or condition the electrical signal to produce a detector output. The systems and methods disclosed herein attenuate the power level of an incoming communication beam to prevent oversaturation of an APD. The system further provides an alignment signal, which is effective over a wide dynamic range of incoming power levels.
摘要:
The disclosed method for forming a field emission display includes forming a cathode and an anode, forming a plurality of photoresist posts over the cathode, and coating the posts with a layer of coating material. The layer of coating material forms sidewalls around the posts. The photoresist posts may then be removed from within the sidewalls. The anode may then be fitted onto the sidewalls so that the sidewalls function as spacers in the field emission display.
摘要:
A system and method for use with an optical communication beam of light is disclosed. The system allows the beam of light to operate at an adequate power level that provides a robust optical link while minimizing any safety risk to humans. Such a system includes multiple operating modes which control the power output of the beam of light. In the normal mode, the beam of light operates at a selected power level which provides a desired signal to noise ratio. Once a blocking occurs, the beam of light enters a power reduction mode to prevent harm to the blocking object. An acquisition and recovery mode is then employed to reestablish the blocked communication link.
摘要:
A substrate is placed on a charging surface, to which a first voltage is applied. Etch-resistant dry particles are placed in a cup in a nozzle to which a second voltage, less than the first voltage, is applied. A carrier gas is directed through the nozzle, which projects the dry particles out of the nozzle toward the substrate. The particles pick up a charge from the potential applied to the nozzle and are electrostatically attracted to the substrate. The particles adhere to the substrate, where they form an etch mask. The substrate is etched and the particles are removed. Emitter tips for a field emission display may be formed in the substrate.
摘要:
A process for fabricating a flat panel display having a faceplate and a baseplate comprises creating an electric field between the faceplate and the baseplate to temporarily attract the faceplate to the baseplate and attaching the baseplate and faceplate to each other while the electric field is present. Capacitor(s) are formed on the faceplate and/or baseplate of a flat panel display such that a portion of the capacitor(s) is formed on the faceplate and is aligned with the pixel matrix and/or a portion of the capacitor(s) is formed on the baseplate and is aligned with the cathode member. The first and second portions of the capacitor(s) are energized to opposite polarity voltages, and an electric field is generated which attracts and aligns the two portions of the capacitor(s) to each other. When the two portions of the capacitor(s) are aligned and attracted to each other, the pixel matrix and cathode assembly are inherently aligned with each other. Once the faceplate and the baseplate are attached to each other, the capacitor(s) are de-energized and the electric field is dissipated.
摘要:
The present disclosure describes microelectronic substrate assemblies, and methods for making and using such substrate assemblies in mechanical and chemical-mechanical planarizing processes. A microelectronic substrate assembly is fabricated in accordance with one aspect of the invention by forming a critical layer in a film stack on the substrate and manipulating the critical layer to have a low compression internal stress. The critical layer, more specifically, is a layer that is otherwise in a tensile state or a high compression state without being manipulated to control the internal stress in the critical layer to be in a low compression state. The stress in the critical layer can be manipulated by changing the chemistry, temperature or energy level of the process used to deposit or otherwise form the critical layer. The stress in the critical layer can also be manipulated using heat treatments and other processes. A critical layer composed of chromium, for example, can be manipulated by sputtering chromium in an argon/nitrogen atmosphere instead of solely an argon atmosphere to impart stress controlling elements (nitrogen molecules) into the chromium for producing a low compression chromium layer.
摘要:
In one aspect, the invention includes a method of fabricating a flat panel evacuated display. An oxidizable material layer is formed over a substrate upper surface. The oxidizable material has an upper surface and is provided as a plurality of separate discrete elements. A layer of sacrificial material is formed over the oxidizable material upper surface and over intervening regions of the substrate between the separate discrete elements. The sacrificial material is selectively removable relative to the oxidizable material. The layer of sacrificial material is planarized to remove the sacrificial material from over the oxidizable material upper surface. A plurality of spacers are bonded to the oxidizable material upper surface. The sacrificial material is removed from between the separate discrete elements.
摘要:
A method for fabricating microelectronic deices in which an interconnect layer is electrically isolated from large protuberances that project from a lower conductive layer to a desired endpoint of a chemical-mechanical planarization process. The lower conductive layer is covered with an insulating material to form an insulator layer that generally follows the contour of the lower conductive layer and any large protuberances. A highly conductive interconnect material is then deposited over the insulator layer to form an interconnect layer that generally follows the contour of the insulator layer. The interconnect layer may be deposited directly on the insulator layer, or it may be deposited on an intermediate layer between the interconnect layer and the insulator layer. After the upper conductive layer is deposited, the insulator layer and the upper conductive layer are planarized with a chemical-mechanical planarization process to a desired endpoint.
摘要:
A method for forming spacers for a display device includes steps of contacting a substrate of one of a cathode and a faceplate substrate with a member, drawing the member from the substrate to form a filament, and detaching the member from the filament. The filament can be further planarized to a desired height and shape. The filament extends to the other of the cathode and faceplate.