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公开(公告)号：US20080106926A1
公开(公告)日：2008-05-08
申请号：US11937479
申请日：2007-11-08
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/24 , G11C13/0007 , G11C2213/32 , G11C2213/53 , G11C2213/72 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L29/685 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.
摘要翻译： 一种集成电路存储单元，包括：具有第一有源区，第二有源区和在有源区之间的沟道的半导体; 以及在通道正上方的可变电阻材料层（VRM）。 在一个实施例中，在VRM和沟道之间存在第一导电层，以及VRM层正上方的第二导电层。 VRM优选为相关电子材料（CEM）。 存储单元包括FET，例如JFET或MESFET。 在另一个实施例中，在VRM和通道之间存在绝缘材料层。 在这种情况下，存储单元可以包括MOSFET结构。
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公开(公告)号：US07639523B2
公开(公告)日：2009-12-29
申请号：US11937480
申请日：2007-11-08
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1641 , H01L45/1675
摘要： A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.
摘要翻译： 一种非易失性电阻式开关存储器，其包括在绝缘和导电状态之间变化的材料。 该材料通过外部配体如碳稳定，防止由氧空位的电荷捕获。
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公开(公告)号：US07872900B2
公开(公告)日：2011-01-18
申请号：US11937461
申请日：2007-11-08
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A non-volatile resistive switching memory that includes a homogeneous material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.
摘要翻译： 一种非易失性电阻式开关存储器，其包括由于电子之间的相关性而导致的绝缘和导电状态之间的均匀材料，特别是通过Mott跃迁。 该材料结晶成导电状态，不需要电铸。
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44.发明申请公开(公告)号：US20100283028A1
公开(公告)日：2010-11-11
申请号：US12840870
申请日：2010-07-21
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/24 , G11C13/0007 , G11C2213/32 , G11C2213/53 , G11C2213/72 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L29/685 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.
摘要翻译： 一种集成电路存储单元，包括：具有第一有源区，第二有源区和在有源区之间的沟道的半导体; 以及在通道正上方的可变电阻材料层（VRM）。 在一个实施例中，在VRM和沟道之间存在第一导电层，以及VRM层正上方的第二导电层。 VRM优选为相关电子材料（CEM）。 存储单元包括FET，例如JFET或MESFET。 在另一个实施例中，在VRM和通道之间存在绝缘材料层。 在这种情况下，存储单元可以包括MOSFET结构。
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公开(公告)号：US07778063B2
公开(公告)日：2010-08-17
申请号：US11937479
申请日：2007-11-08
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/24 , G11C13/0007 , G11C2213/32 , G11C2213/53 , G11C2213/72 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L29/685 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.
摘要翻译： 一种集成电路存储单元，包括：具有第一有源区，第二有源区和在有源区之间的沟道的半导体; 以及在通道正上方的可变电阻材料层（VRM）。 在一个实施例中，在VRM和沟道之间存在第一导电层，以及VRM层正上方的第二导电层。 VRM优选为相关电子材料（CEM）。 存储单元包括FET，例如JFET或MESFET。 在另一个实施例中，在VRM和通道之间存在绝缘材料层。 在这种情况下，存储单元可以包括MOSFET结构。
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公开(公告)号：US20100090172A1
公开(公告)日：2010-04-15
申请号：US12618596
申请日：2009-11-13
IPC分类号： H01B1/02
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1641
摘要： A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.
摘要翻译： 一种非易失性电阻式开关存储器，其包括在绝缘和导电状态之间变化的材料。 该材料通过外部配体如碳稳定，防止由氧空位的电荷捕获。
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公开(公告)号：US06562678B1
公开(公告)日：2003-05-13
申请号：US09521094
申请日：2000-03-07
IPC分类号： H01L218242
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
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48.发明授权Chemical vapor deposition method of making layered superlattice materials using trimethylbismuth 失效使用三甲基铋制备层状超晶格材料的化学气相沉积方法公开(公告)号：US06787181B2
公开(公告)日：2004-09-07
申请号：US10007119
申请日：2001-10-26
IPC分类号： B05D512
CPC分类号： H01L21/02205 , C23C16/40 , C30B25/02 , C30B29/02 , C30B29/68 , H01L21/02194 , H01L21/02197 , H01L21/02271 , H01L21/31691 , H01L28/55
摘要： A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650° C. or higher are used.
摘要翻译： 使用溶解在有机溶剂中的三甲基铋前体溶液和金属化合物的化学气相沉积在基板上形成双层超晶格材料的方法。 在通过化学气相沉积将前体溶液沉积在集成电路基板上之前，先前溶液被加热和蒸发。 不使用包括650℃或更高的温度的加热步骤。
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49.发明授权Chemical vapor deposition process for fabricating layered superlattice materials 有权用于制造层状超晶格材料的化学气相沉积工艺公开(公告)号：US06706585B2
公开(公告)日：2004-03-16
申请号：US10405309
申请日：2003-04-02
IPC分类号： H01L218242
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
摘要翻译： 第一反应气体流入含有加热集成电路基板的CVD反应室。 第一反应气体含有第一前体化合物或多个第一前体化合物，第一前体化合物或化合物在CVD反应室中分解，以在被加热的集成电路衬底上沉积含有金属原子的涂层。 涂层用RTP处理。 此后，将第二反应气体流入含有加热衬底的CVD反应室。 第二反应气体含有第二前体化合物或多个第二前体化合物，其在CVD反应室中分解以在基底上沉积更多的金属原子。 通过在CVD沉积期间以及通过选择的快速热处理（“RTP”）和炉退火步骤加热衬底来提供沉积的金属原子以形成层状超晶格材料的薄膜的反应和结晶的热。
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50.发明授权Low temperature rapid ramping anneal method for fabricating layered superlattice materials and making electronic devices including same 有权用于制造分层超晶格材料的低温快速斜面退火方法，并制造包括它们的电子器件公开(公告)号：US06326315B1
公开(公告)日：2001-12-04
申请号：US09523919
申请日：2000-03-09
IPC分类号： H01L2131
CPC分类号： H01L21/28291 , C30B7/00 , C30B7/005 , C30B29/68
摘要： A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.
摘要翻译： 用于形成层状超晶格材料的液体前体被施加到集成电路基板。 使用快速斜面退火（“RRA”）技术将前体涂层在氧气中退火，在650℃的保持温度下以50℃/秒的升高速率保持30分钟的保持时间。
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