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19 条记录 (耗时 0.022 秒)

    Chemical vapor deposition process for fabricating layered superlattice materials
    3.
    发明授权
    Chemical vapor deposition process for fabricating layered superlattice materials 有权

    公开(公告)号：US06562678B1

    公开(公告)日：2003-05-13

    申请号：US09521094

    申请日：2000-03-07

    申请人： Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

    发明人： Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

    IPC分类号： H01L218242

    CPC分类号： C23C16/45561 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/44 ,  Y10S438/935 ,  Y10S438/938

    摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

    Chemical vapor deposition process for fabricating layered superlattice materials
    5.
    发明授权
    Chemical vapor deposition process for fabricating layered superlattice materials 有权
    用于制造层状超晶格材料的化学气相沉积工艺

    公开(公告)号：US06706585B2

    公开(公告)日：2004-03-16

    申请号：US10405309

    申请日：2003-04-02

    申请人： Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

    发明人： Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

    IPC分类号： H01L218242

    CPC分类号： C23C16/45561 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/44 ,  Y10S438/935 ,  Y10S438/938

    摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

    摘要翻译： 第一反应气体流入含有加热集成电路基板的CVD反应室。 第一反应气体含有第一前体化合物或多个第一前体化合物，第一前体化合物或化合物在CVD反应室中分解，以在被加热的集成电路衬底上沉积含有金属原子的涂层。 涂层用RTP处理。 此后，将第二反应气体流入含有加热衬底的CVD反应室。 第二反应气体含有第二前体化合物或多个第二前体化合物，其在CVD反应室中分解以在基底上沉积更多的金属原子。 通过在CVD沉积期间以及通过选择的快速热处理（“RTP”）和炉退火步骤加热衬底来提供沉积的金属原子以形成层状超晶格材料的薄膜的反应和结晶的热。

    Method of making ferroelectric material utilizing anneal in an electrical field
    7.
    发明授权
    Method of making ferroelectric material utilizing anneal in an electrical field 失效
    在电场中利用退火制造铁电材料的方法

    公开(公告)号：US06660536B2

    公开(公告)日：2003-12-09

    申请号：US10080383

    申请日：2002-02-21

    申请人： Kiyoshi Uchiyama ,  Carlos A. Paz de Araujo

    发明人： Kiyoshi Uchiyama ,  Carlos A. Paz de Araujo

    IPC分类号： H01L2100

    CPC分类号： H01L27/10852 ,  H01L21/02197 ,  H01L21/3105 ,  H01L27/10808 ,  H01L28/55

    摘要： A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.

    摘要翻译： 铁电薄膜前体材料在电场中退火。 当材料冷却时，保持电场。 具有铁电薄膜前体材料的部分完成的集成电路可以在退火装置中放置在两个电极之间，并且在退火期间将足以使铁电薄膜材料沿电场方向偏振的电压供应到电极，并且作为 电影冷却 或者，探针连接到部分完成的集成电路器件的电极，并且在退火材料并且在其冷却时施加足以极化铁电材料的电压。 退火可以是炉退火或RTP退火。

    Semiconductor memory device, method for driving the same and method for fabricating the same
    8.
    发明授权
    Semiconductor memory device, method for driving the same and method for fabricating the same 失效
    半导体存储器件，其驱动方法及其制造方法

    公开(公告)号：US06580632B2

    公开(公告)日：2003-06-17

    申请号：US09782300

    申请日：2001-02-14

    申请人： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    发明人： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    IPC分类号： G11C1122

    CPC分类号： H01L29/516 ,  G11C11/22 ,  G11C11/223 ,  H01L29/78391

    摘要： Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data “1” while the up or almost zero remnant polarization may represent data “0”, for example. By regarding the almost zero remnant polarization state as representing data “0”, a read current value becomes substantially constant in the data “0” state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data “1”) is induced in advance, then the read accuracy further improves.

    摘要翻译： 从强电介质薄膜读​​出数据，其剩余极化与数据的两种可能的逻辑状态之一相关，并且施加到铁电体膜上的控制栅电极上的偏置电压。 铁电薄膜产生上或下残余极化。 因此，向下残留极化可以表示数据“1”，而上或近零残余极化例如可以表示数据“0”。 通过将几乎为零的残余极化状态作为表示数据“0”，读取的电流值在数据“0”状态下变得基本恒定。 结果，读取精度提高。 此外，如果预先诱导一个特定逻辑状态（例如，数据“1”）的印记，则读取精度进一步提高。

    Semiconductor memory and method of driving semiconductor memory
    10.
    发明授权
    Semiconductor memory and method of driving semiconductor memory 失效
    半导体存储器和驱动半导体存储器的方法

    公开(公告)号：US06396095B1

    公开(公告)日：2002-05-28

    申请号：US09869522

    申请日：2001-06-29

    申请人： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    发明人： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

    IPC分类号： H01L2976

    CPC分类号： G11C11/22 ,  H01L21/28291 ,  H01L29/42324 ,  H01L29/516 ,  H01L29/78391

    摘要： Source/drain regions for a field effect transistor are defined in a semiconductor substrate with a channel region interposed therebetween. A first gate electrode is formed over the semiconductor substrate with an insulating film sandwiched therebetween and has a gate length shorter than the length of the channel region. A ferroelectric film is formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film. A second gate electrode is formed to cover the ferroelectric film.

    摘要翻译： 用于场效应晶体管的源极/漏极区限定在其间插入沟道区的半导体衬底中。 第一栅电极形成在半导体衬底之上，绝缘膜夹在其间，栅极长度短于沟道区的长度。 形成铁电膜以覆盖第一栅电极并且使其两侧部分与绝缘膜接触。 形成第二栅电极以覆盖铁电体膜。