公开(公告)号：US06617226B1

公开(公告)日：2003-09-09

申请号：US09609107

申请日：2000-06-30

申请人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L2120

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US20120309207A1

公开(公告)日：2012-12-06

申请号：US13473817

申请日：2012-05-17

申请人： Koji AKIYAMA ,  Hirokazu Higashijima ,  Yoshitsugu Tanaka ,  Yasushi Akasaka ,  Koji Yamashita

发明人： Koji AKIYAMA ,  Hirokazu Higashijima ,  Yoshitsugu Tanaka ,  Yasushi Akasaka ,  Koji Yamashita

IPC分类号： H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/26566 ,  H01L21/28185 ,  H01L29/517

摘要： A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.

摘要翻译： 公开的半导体器件的制造方法包括以下步骤：在半导体衬底上沉积电介质膜; 对电介质膜进行热处理; 并将电离气体簇照射到热处理的电介质膜上。

公开(公告)号：US07718497B2

公开(公告)日：2010-05-18

申请号：US12130296

申请日：2008-05-30

申请人： Yasushi Akasaka ,  Noriaki Fukiage ,  Yoshihiro Kato ,  Kazuhide Hasebe ,  Pao-Hwa Chou

发明人： Yasushi Akasaka ,  Noriaki Fukiage ,  Yoshihiro Kato ,  Kazuhide Hasebe ,  Pao-Hwa Chou

IPC分类号： H01L21/8234

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which readily etches the unreacted portion of the metal film and the sidewall spacer while hardly etching the device isolation region, resistance-reduced portions of the gate electrode and resistance-reduced portions of the source and drain regions.

摘要翻译： 半导体器件制造方法包括：在栅电极的侧壁表面上形成侧壁间隔物; 在有源区中形成一对第二导电型源区和漏区; 用金属膜覆盖半导体层的顶表面，器件隔离区，侧壁间隔物和栅电极; 通过使金属膜与半导体层和栅极电极反应，部分地降低源极和漏极区域和栅电极的电阻; 并且通过使用易于蚀刻金属膜和侧壁间隔物的未反应部分的蚀刻剂同时去除金属膜和侧壁间隔物的未反应部分，同时几乎不蚀刻器件隔离区域，栅电极的电阻减少部分和电阻 - 源区和漏区的部分。

公开(公告)号：US20080299728A1

公开(公告)日：2008-12-04

申请号：US12130296

申请日：2008-05-30

申请人： Yasushi Akasaka ,  Noriaki Fukiage ,  Yoshihiro Kato ,  Kazuhide Hasebe ,  Pao-Hwa Chou

发明人： Yasushi Akasaka ,  Noriaki Fukiage ,  Yoshihiro Kato ,  Kazuhide Hasebe ,  Pao-Hwa Chou

IPC分类号： H01L21/8236

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which readily etches the unreacted portion of the metal film and the sidewall spacer while hardly etching the device isolation region, resistance-reduced portions of the gate electrode and resistance-reduced portions of the source and drain regions.

摘要翻译： 半导体器件制造方法包括：在栅电极的侧壁表面上形成侧壁间隔物; 在有源区中形成一对第二导电型源区和漏区; 用金属膜覆盖半导体层的顶表面，器件隔离区，侧壁间隔物和栅电极; 通过使金属膜与半导体层和栅极电极反应，部分地降低源极和漏极区域和栅电极的电阻; 并且通过使用易于蚀刻金属膜和侧壁间隔物的未反应部分的蚀刻剂同时去除金属膜和侧壁间隔物的未反应部分，同时几乎不蚀刻器件隔离区域，栅电极的电阻减少部分和电阻 - 源区和漏区的部分。

公开(公告)号：US07432147B2

公开(公告)日：2008-10-07

申请号：US11318479

申请日：2005-12-28

申请人： Yasushi Akasaka

发明人： Yasushi Akasaka

IPC分类号： H01L21/8238

CPC分类号： H01L29/518 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film; forming a region of a second metal film so as to cover a region that forms a gate electrode of the first conductivity type region; removing the first metal film exposed outside the region of the second metal film by wet etching to expose the gate insulating film; forming a third metal film on the entire surface of the semiconductor substrate; depositing a protecting film on the third metal film; and patterning the first metal film, the second metal film, the third metal film, and the protecting film to form the gate electrode.

摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底上形成器件隔离，第一导电类型区域和第二导电类型区域; 在半导体衬底的整个表面上沉积栅极绝缘膜; 在栅极绝缘膜上形成第一金属膜; 形成第二金属膜的区域，以覆盖形成第一导电类型区域的栅电极的区域; 通过湿蚀刻去除暴露在第二金属膜的区域外的第一金属膜，以露出栅极绝缘膜; 在半导体衬底的整个表面上形成第三金属膜; 在第三金属膜上沉积保护膜; 以及图案化第一金属膜，第二金属膜，第三金属膜和保护膜以形成栅电极。

公开(公告)号：US20070190767A1

公开(公告)日：2007-08-16

申请号：US11673218

申请日：2007-02-09

申请人： Genji Nakamura ,  Yasushi Akasaka

发明人： Genji Nakamura ,  Yasushi Akasaka

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/823835 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method for manufacturing a semiconductor device, an insulating film is formed on an entire surface of a substrate having a device isolation region and a first and a second conductive region. Then, a semiconductor device structure having a gate electrode forming region is formed on each of the conductive regions, the insulating film being disposed between the gate electrode forming region and each of the conductive regions. A gate electrode groove is formed in the gate electrode forming region of the semiconductor device structure, the insulating film being removed in the gate electrode groove. Thereafter, a gate insulating film and a film of metal gate electrode material are deposited on a bottom surface and a side surface of the gate electrode groove and an alloy is formed by alloying the film of metal gate electrode material deposited in a gate electrode groove of the first conductive region.

摘要翻译： 在制造半导体器件的方法中，在具有器件隔离区域和第一和第二导电区域的衬底的整个表面上形成绝缘膜。 然后，在每个导电区域上形成具有栅极形成区域的半导体器件结构，绝缘膜设置在栅极形成区域和每个导电区域之间。 在半导体器件结构的栅电极形成区域中形成栅极电极沟槽，在栅极电极沟槽中去除绝缘膜。 此后，栅极绝缘膜和金属栅电极膜沉积在栅电极沟槽的底表面和侧表面上，合金通过将沉积在栅极电极沟槽中的金属栅电极材料的膜合金化而形成 第一导电区域。

公开(公告)号：US20060081939A1

公开(公告)日：2006-04-20

申请号：US11222139

申请日：2005-09-09

申请人： Yasushi Akasaka ,  Kazuhiro Miyagawa ,  Takaoki Sasaki

发明人： Yasushi Akasaka ,  Kazuhiro Miyagawa ,  Takaoki Sasaki

IPC分类号： H01L29/76

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/7833

摘要： A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with increased electron mobility and enhanced hole mobility is disclosed. In this semiconductor device, a p-type well layer and an n-type well layer are formed in a surface portion of a silicon substrate. A nitrogen-nondoped n-channel interface layer and a nitrogen-free n-channel high dielectric constant gate insulation film plus an n-channel gate electrode are formed in an n-channel MISFET as partitioned by an element isolation region. And, n-type source/drain diffusion layers are provided. In a p-channel MISFET, a nitrogen-doped p-channel interface layer, a nitrogen-added p-channel high dielectric gate insulation film and a p-channel gate electrode are formed along with p-channel source/drain diffusion layers as provided therein. A method of fabricating this semiconductor device is also disclosed.

摘要翻译： 公开了具有增加的电子迁移率和增加的空穴迁移率的金属绝缘体半导体场效应晶体管（MISFET）的半导体器件。 在该半导体器件中，在硅衬底的表面部分中形成p型阱层和n型阱层。 在由元件隔离区分隔的n沟道MISFET中形成氮 - 非掺杂的n沟道界面层和无氮n沟道高介电常数栅极绝缘膜加上n沟道栅电极。 并且，提供n型源极/漏极扩散层。 在p沟道MISFET中，与所提供的p沟道源极/漏极扩散层一起形成氮掺杂p沟道界面层，添加氮的p沟道高介电栅极绝缘膜和p沟道栅电极 其中。 还公开了一种制造该半导体器件的方法。

公开(公告)号：US5698881A

公开(公告)日：1997-12-16

申请号：US353240

申请日：1994-12-02

申请人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

发明人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/0338 ,  H01L21/2255 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66628

摘要： A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

摘要翻译： MOS型半导体器件具有长度为170nm（0.17μm）以下的栅极，沟道附近的源极和漏极扩散层的结深度为22nm以下，表面上的杂质浓度 在源极和漏极扩散层中形成1020cm-3以上。 这种结构使用从950℃到1050℃的热范围的固相扩散和/或通过灰化或蚀刻使栅极宽度变窄来获得。 其他MOS型半导体器件的特征在于源极和漏极扩散层区域中的结深度xj [nm]与有效沟道长度Leff [nm]之间的关系由Leff> 0.69×j-6.17确定。