Semiconductor memory device and a method of manufacturing the same
    42.
    发明授权
    Semiconductor memory device and a method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US07981738B2

    公开(公告)日:2011-07-19

    申请号:US12909878

    申请日:2010-10-22

    IPC分类号: H01L21/8238 H01L21/8234

    摘要: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

    摘要翻译: SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。 垂直MISFET分别主要包括由下半导体层,中间半导体层和按此顺序层叠的上半导体层形成的层压体,形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜和栅电极 形成为覆盖层压体的侧壁。 垂直MISFET是完全耗尽型MISFET。

    Semiconductor integrated circuitry and method for manufacturing the circuitry
    49.
    发明申请
    Semiconductor integrated circuitry and method for manufacturing the circuitry 有权
    半导体集成电路和制造电路的方法

    公开(公告)号:US20050017274A1

    公开(公告)日:2005-01-27

    申请号:US10920389

    申请日:2004-08-18

    摘要: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

    摘要翻译: 用于半导体集成电路的技术允许每个DRAM存储单元被细分,以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中,首先,在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7,并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后,在DRAM存储单元区域中的选择MISFET Qs中,相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21,并且连接部分形成为将导体20连接到位线BL 。 此外,在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中,形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。