公开(公告)号：US20070241394A1

公开(公告)日：2007-10-18

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62.栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US06603173B1

公开(公告)日：2003-08-05

申请号：US09391236

申请日：1999-09-07

申请人： Yoshifumi Okabe ,  Yoshihiko Ozeki ,  Shigeki Takahashi ,  Norihito Tokura

发明人： Yoshifumi Okabe ,  Yoshihiko Ozeki ,  Shigeki Takahashi ,  Norihito Tokura

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236

摘要： A vertical power MOSFET, which can improve a surge withstand voltage and a surge withstand voltage against a surge voltage from an inductance load L. The vertical power MOSFET has a plurality of unit cells. The unit cell is formed from a MOSFET that uses a p-type base layer at a sidewall of a rectangular U-groove as a channel portion. Each of the p-type base layer of each unit cell is connected each others Accordingly, it can restrain an impurity concentration of a corner portion (a portion positioned at a corner) of the rectangular p-type base layer from being decreased. Therefore, it can reduce the difference in distance from the end portion of the p-type base layer to the end portion of the depletion layer. As a result, it can improve the surge withstand voltage when a surge voltage is input from an inductance load L.

摘要翻译： 一种垂直功率MOSFET，其可以提高抗电压耐受电压和抵抗来自电感负载L的浪涌电压的浪涌耐受电压。垂直功率MOSFET具有多个单元电池。 单位电池由在矩形U形槽的侧壁处使用p型基底层作为沟道部分的MOSFET形成。 每个单电池的p型基极层彼此连接。因此，能够抑制矩形p型基极层的角部（位于角部的部分）的杂质浓度降低。 因此，可以减少与p型基底层的端部到耗尽层的端部的距离的差异。 因此，当从电感负载L输入浪涌电压时，可以提高浪涌耐受电压。

公开(公告)号：US6072240A

公开(公告)日：2000-06-06

申请号：US174171

申请日：1998-10-16

申请人： Tomonori Kimura ,  Norihito Tokura ,  Fumio Ohara ,  Masahito Mizukoshi

发明人： Tomonori Kimura ,  Norihito Tokura ,  Fumio Ohara ,  Masahito Mizukoshi

IPC分类号： H01L25/07 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/072 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

摘要翻译： 即使当半导体芯片具有易受应力的结构时，也能够提高散热性能，实现尺寸的降低，能够迅速地从半导体芯片的两个主面散热。 它包括几个IGBT芯片，每个IGBT芯片在一个主表面上具有集电极电极，在另一个主表面上具有发射极电极和栅极电极，并且两个高导热绝缘基板夹在这些IGBT芯片上，并具有用于接合到IGBT的电极的电极图案 设置在其夹层表面上的芯片，IGBT芯片的电极和高导热绝缘基板的电极图案通过钎焊粘结。

公开(公告)号：US6020600A

公开(公告)日：2000-02-01

申请号：US938805

申请日：1997-09-26

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/66068 ,  H01L29/7828 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  Y10S438/981

摘要： A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n.sup.+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n.sup.+ type silicon carbide semiconductor substrate 1.

摘要翻译： 提供了具有高阻断电压，低损耗和低阈值电压的碳化硅半导体器件。 n +型碳化硅半导体衬底1，n型碳化硅半导体衬底2和p型碳化硅半导体层3相互层叠在一起。 在p型碳化硅半导体层3的表面的预定区域中形成n +型源极区6，并且形成沟槽9，以延伸穿过n +型源极区6和p型碳化硅半导体层 在n型碳化硅半导体层2的表面上延伸设置有薄膜半导体层（n型或p型）11a，在n +型源极区6，p型碳化硅半导体层3的表面上， 在沟槽9的侧面中的n型碳化硅半导体层2.栅极电极层13通过沟槽9内的栅极绝缘层12设置。源电极层15设置在p型表面上 碳化硅半导体层3和n +型源极区6的表面，以及在n +型碳化硅半导体衬底1的表面上设置漏电极层16。

公开(公告)号：US5973338A

公开(公告)日：1999-10-26

申请号：US947402

申请日：1997-10-08

申请人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

发明人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

摘要翻译： 绝缘栅型双极晶体管（IGBT）在整体结构中包含过电压保护功能和漏极电压固定功能。 杂质浓度ND和n型漏极层（3）的厚度被设定为使得从ap型基极层（7）传播的耗尽区域在低于电压（VDSS）的VDSP下达到p +型漏极层 ），当在源极和漏极之间施加电压时，在IGBT元件内引起雪崩击穿。

公开(公告)号：US5915180A

公开(公告)日：1999-06-22

申请号：US418147

申请日：1995-04-05

申请人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

发明人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/931

摘要： A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench. A gate electrode layer is provided on the surface of the oxide layer, formed by thermal oxidation, within the trench, a source electrode layer is provided on the epitaxial layer and the source region, and a drain electrode layer is provided on the back surface of the semiconductor substrate.

摘要翻译： 具有其厚度的氧化物紫菜的半导体器件可以从沟槽的内表面的一部分变化，并且可以容易地制造，以及其制造方法。 n +型单晶SiC衬底由具有（0001）面取向的碳面作为表面的六方晶系的SiC形成，并且n型外延层和p型外延层依次层叠在衬底上。 在p型外延层内提供n +源极区，并且沟槽延伸穿过源区和外延层进入半导体衬底。 沟槽的侧面几乎垂直于外延层的表面，沟槽的底面具有平行于外延层的表面的平面。 在沟槽的底面上通过热氧化形成的栅极氧化物层的厚度大于沟槽侧面上的栅极氧化物层的厚度。 在氧化层形成的氧化层的表面上，在沟槽内设置栅极电极层，在外延层和源极区域设置有源电极层，在其背面设有漏电极层 半导体衬底。

公开(公告)号：US5696396A

公开(公告)日：1997-12-09

申请号：US734132

申请日：1996-10-21

申请人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

发明人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76 ,  H01L31/0312 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7802

摘要： A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.- silicon layer to be negligibly small as compared with the current flowing from the source terminal through the source electrode to the n.sup.+ source region, the channel region and the n.sup.- silicon layer.

摘要翻译： 可以获得只能通过栅极电压控制流过器件的交流电流的垂直MOSFET。 在n +硅层上形成n-硅层。 在n-硅层内形成p体区域。 在p体区内形成n +源区。 在基板顶部形成仅与源极区域接触的源极电极和仅与p体区域接触的基极电极。 源电极和基极通过外部的电阻彼此连接。 在沟道区域上通过栅极氧化膜（绝缘膜）形成栅电极。 当上述半导体器件处于反向偏压传导时，通过将从源极端子流过电流的电流设置到基极，p体区域和n-硅层，从而仅通过栅极电压来控制励磁电流 与源极端子通过源极电极流到n +源极区域，沟道区域和n-硅层的电流相比，可以忽略不计。

公开(公告)号：US5608616A

公开(公告)日：1997-03-04

申请号：US351027

申请日：1994-12-07

申请人： Atsushi Umeda ,  Norihito Tokura ,  Hirohide Sato

发明人： Atsushi Umeda ,  Norihito Tokura ,  Hirohide Sato

IPC分类号： H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H02J7/14 ,  H02K1/22 ,  H02K11/04 ,  H02K21/04 ,  H02M7/00 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/7803 ,  H02J7/1492 ,  H02K11/046 ,  H02M7/003 ,  H01L29/45 ,  Y02T10/92

摘要： A power converter for an AC generator for motor vehicles for converting a generated voltage of the AC generator driven by an engine into a DC voltage to feed to a battery includes at least either high-side MOS power transistors for connecting an output end of an armature coil which generates the generated voltage of the AC generator with a high potential end of a battery or low-side MOS power transistors for connecting the output end of the armature coil with a low potential end of the battery. The MOS power transistors each has a source region, a well region and a drain region. A high resistance connected with either a parasitic diode on the side connected with the source generated between the source region and well region or a parasitic diode on the side connected with the drain generated between the drain region and well region in parallel is formed in the MOS power transistors. Thereby, it allows blocking a reverse current produced by the parasitic diode and giving a necessary potential to the well region. Further, SiC is used in the MOS power transistors rather than Si.

摘要翻译： 一种用于机动车辆的交流发电机的电力转换器，用于将由发动机驱动的交流发电机的发电电压转换为直流电压以供电至电池，至少包括用于连接电枢的输出端的高侧MOS功率晶体管 线圈，其产生具有用于将电枢线圈的输出端与电池的低电位端连接的电池或低侧MOS功率晶体管的高电位端的交流发电机的发电电压。 MOS功率晶体管各自具有源极区，阱区和漏极区。 在源极区域和阱区域之间产生的与源极连接的一侧的寄生二极管或与漏极区域和阱区域之间并联产生的漏极侧的寄生二极管并联连接的高电阻形成在MOS 功率晶体管。 因此，它允许阻挡由寄生二极管产生的反向电流并为阱区提供必要的电位。 此外，SiC用于MOS功率晶体管而不是Si。

公开(公告)号：US5453390A

公开(公告)日：1995-09-26

申请号：US38958

申请日：1993-03-29

申请人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

发明人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L21/266

CPC分类号： H01L29/66712 ,  H01L27/0248 ,  H01L29/7811 ,  H01L29/7815 ,  Y10S148/126

摘要： A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.

摘要翻译： 一种具有电流检测功能的功率半导体器件，包括具有比主要电流部分更好的达到耐受电压能力的元件的检测灵敏度。 功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。 设备的一个区域作为检测部分，另一个作为主要的当前部分。 检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。 低密度层的表面分别载有第二导电类型的主要和次要的阱区。 主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。 通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。 这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

公开(公告)号：US5448092A

公开(公告)日：1995-09-05

申请号：US70362

申请日：1993-06-01

申请人： Naoto Okabe ,  Norihito Tokura

发明人： Naoto Okabe ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/00 ,  H01L29/74

CPC分类号： H01L29/7395 ,  H01L27/0248 ,  H01L29/1095

摘要： An insulated gate bipolar transistor (IGBT) element has a current detection function. An impurity-diffused area is formed at an area different from a unit cell area on the surface of the element. The current detection is performed by detecting a voltage drop due to carriers flowing in the lateral resistance of the impurity-diffused area. For example, in an n-channel IGBT, electrons are injected from a source electrode through an n-type source layer and the channel to an n-type drain layer at the cell when the unit cell is in an on-state. The pn junction at the drain side is forwardly biased to inject holes from the p-type drain layer to the n-type drain layer. At this time, the electrons also flow to the lower side of the p-type impurity-diffused area provided as the detection portion. Thus, the hole injection occurs at this portion. These surplus holes are discharged through the p-type layer of the detection portion to the source electrode. A potential which corresponds to a product of the lateral resistance of the p-type layer and a hole current appears at the source potential. By detecting this potential and converting the detected potential, an element current can be detected.

摘要翻译： PCT No.PCT / JP92 / 01239 Sec。 371日期：1993年6月1日 102（e）日期1993年6月1日PCT 1992年9月28日PCT公布。 出版物WO93 / 07645 日期：1993年04月15日。绝缘栅双极晶体管（IGBT）元件具有电流检测功能。 在与元件表面上的单元电池区域不同的区域上形成杂质扩散区域。 通过检测由于在杂质扩散区域的横向电阻中流动的载流子的电压降而进行电流检测。 例如，在n沟道IGBT中，当单位电池处于导通状态时，电子从源电极通过n型源极层和沟道注入到单元的n型漏极层。 漏极侧的pn结被向前偏置以从p型漏极层向n型漏极层注入空穴。 此时，电子也流到作为检测部设置的p型杂质扩散区域的下侧。 因此，在该部分发生空穴注入。 这些剩余的孔通过检测部的p型层被排出到源电极。 对应于p型层的横向电阻和空穴电流的乘积的电位出现在电位电位。 通过检测该电位并转换检测到的电位，可以检测元件电流。