Strained tri-channel layer for semiconductor-based electronic devices
    42.
    发明授权
    Strained tri-channel layer for semiconductor-based electronic devices 有权
    用于基于半导体的电子器件的应变三沟道层

    公开(公告)号:US07791107B2

    公开(公告)日:2010-09-07

    申请号:US10869463

    申请日:2004-06-16

    IPC分类号: H01L21/3205

    摘要: A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.

    摘要翻译: 基于半导体的结构包括衬底层,与衬底层相邻的压缩应变半导体层以提供用于部件的沟道,以及布置在衬底层和压缩应变半导体层之间的拉伸应变半导体层。 一种制造电子器件的方法包括在应变诱导基片上提供第一拉伸应变层,在第一拉伸应变层上形成压缩应变层,以及在压缩应变层上形成第二拉伸应变层。 第一和第二拉伸应变层可以由硅形成,并且压缩应变层可以由硅和锗形成。

    Methods of fabricating dual layer semiconductor devices
    43.
    发明授权
    Methods of fabricating dual layer semiconductor devices 有权
    制造双层半导体器件的方法

    公开(公告)号:US07465619B2

    公开(公告)日:2008-12-16

    申请号:US11130575

    申请日:2005-05-17

    IPC分类号: H01L21/8238

    摘要: A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.

    摘要翻译: 基于半导体的器件包括沟道层,其包括远端层和与远端层接触的近端层。 远端层支撑至少一个p沟道分量的至少一部分空穴传导,并且近端支撑至少一个n沟道分量的至少一部分电子传导。 近端层具有允许空穴波函数从近端层有效地延伸到远侧层中的厚度,以便于远端层的空穴传导。 一种用于制造基于半导体的器件的方法包括提供沟道层的远端部分并提供沟道层的近端部分。

    STRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER
    45.
    发明申请
    STRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER 有权
    具有Ge通道层的高速半导体器件的结构和方法

    公开(公告)号:US20080128747A1

    公开(公告)日:2008-06-05

    申请号:US11877186

    申请日:2007-10-23

    IPC分类号: H01L29/778 H01L21/336

    摘要: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

    摘要翻译: 本发明提供包括应变Ge沟道层的半导体结构和设置在应变Ge沟道层上的栅极电介质。 在本发明的一个方面,提供了应变的Ge沟道MOSFET。 应变Ge沟道MOSFET包括Ge含量在50-95%之间的弛豫SiGe虚拟衬底和形成在虚拟衬底上的应变Ge沟道。 在应变Ge通道上形成栅极结构,于是形成具有在体积Si上增加的性能的MOSFET。 在本发明的另一实施例中,包括松弛的Ge沟道层和虚拟衬底的半导体结构,其中放宽的Ge沟道层设置在虚拟衬底之上。 在本发明的另一方面,提供了一种放宽的Ge沟道MOSFET。 该方法包括提供具有约100%的Ge组成的松弛虚拟衬底和形成在虚拟衬底上的松弛Ge沟道。

    Method for improving hole mobility enhancement in strained silicon p-type MOSFETS
    50.
    发明授权
    Method for improving hole mobility enhancement in strained silicon p-type MOSFETS 有权
    用于改善应变硅p型MOSFET的空穴迁移率增强的方法

    公开(公告)号:US07005668B2

    公开(公告)日:2006-02-28

    申请号:US10603712

    申请日:2003-06-25

    IPC分类号: H01L29/06

    CPC分类号: H01L29/1054 H01L29/165

    摘要: A method of forming a MOSFET device is provided. The method includes providing a substrate. The method includes forming on the substrate a relaxed SiGe layer having a Ge content between 0.51 and 0.80. Furthermore, the method includes depositing on the relaxed SiGe layer a ε-Si layer.

    摘要翻译: 提供了一种形成MOSFET器件的方法。 该方法包括提供基板。 该方法包括在衬底上形成Ge含量在0.51和0.80之间的松弛的SiGe层。 此外,该方法包括在松弛的SiGe层上沉积ε-Si层。