公开(公告)号：US20060289922A1

公开(公告)日：2006-12-28

申请号：US11453796

申请日：2006-06-16

申请人： Naoaki Sudo ,  Kohji Kanamori

发明人： Naoaki Sudo ,  Kohji Kanamori

IPC分类号： H01L29/76

CPC分类号： H01L29/7887 ,  G11C16/0441 ,  G11C16/0491 ,  G11C16/28 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.

摘要翻译： 实现高速可靠的读取操作。 单位电池由设置在第一区域中的选择栅极3和介于其间的绝缘膜2的基板1构成，设置在与第一区域相邻的第二区域中的浮置栅极6a与介于其间的绝缘膜5 设置在与第二区域相邻的第三区域和衬底的表面上的扩散区域7a，以及设置在浮置栅极6a的顶部上的绝缘膜8的控制栅极11。 使用对应的第一单元单元和第二单元单元存储每个数据位。

公开(公告)号：US07064382B2

公开(公告)日：2006-06-20

申请号：US11074064

申请日：2005-03-08

申请人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

发明人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/1033 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7881

摘要： A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

摘要翻译： 非易失性存储器件包括形成在半导体衬底中的源区和漏区，以及形成在半导体衬底中的源区和漏区之间的沟道区上的绝缘膜。 非易失性存储器件还包括形成在通道区域上方以存储电荷的电介质膜，以及形成在电介质膜上的控制栅极。 通道区域的压缩应力为50MPa以下。

公开(公告)号：US20060027853A1

公开(公告)日：2006-02-09

申请号：US11194561

申请日：2005-08-02

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328

摘要： Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.

摘要翻译： 公开了一种半导体存储装置，其在p阱的区域中具有围绕位线扩散区域的沟槽，构成未被字线覆盖的存储单元区域和与字线相交的选择栅极。 绝缘膜被埋在沟槽中。

公开(公告)号：US20050218922A1

公开(公告)日：2005-10-06

申请号：US11088833

申请日：2005-03-25

申请人： Junichi Suzuki ,  Kohji Kanamori

发明人： Junichi Suzuki ,  Kohji Kanamori

IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C16/06 ,  G11C29/00 ,  G11C29/06 ,  H01L21/66 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G01R31/2621

摘要： An apparatus for testing a defect, includes a semiconductor element. In the semiconductor element, a conductive film is formed on an STI (shallow trench isolation) insulating film, which fills a shallow trench extending into a semiconductor region, through an insulating film in an ordinary state, and the shallow trench is not completely or sufficiently filled with the STI insulating film in a defective state. Also, the apparatus includes a control circuit configured to set a test mode in response to a test mode designation signal, a first voltage applying circuit configured to output a first voltage to the conductive film in the test mode, and a second voltage applying circuit configured to output a second voltage to the semiconductor region in the test mode. The first voltage is higher than the second voltage, and a voltage difference between the first voltage and the second voltage is sufficient to cause breakdown between the conductive film and the semiconductor region in the defective state.

摘要翻译： 用于测试缺陷的装置包括半导体元件。 在半导体元件中，在通常通过绝缘膜的STI（浅沟槽隔离）绝缘膜上形成导电膜，其通过绝缘膜填充延伸到半导体区域中的浅沟槽，并且浅沟槽不完全或充分 填充有缺陷状态的STI绝缘膜。 此外，该装置包括：控制电路，被配置为响应于测试模式指定信号设置测试模式;第一电压施加电路，被配置为在测试模式下向导电膜输出第一电压;以及第二电压施加电路， 以在测试模式中向半导体区域输出第二电压。 第一电压高于第二电压，并且第一电压和第二电压之间的电压差足以导致在缺陷状态下导电膜和半导体区域之间的击穿。

公开(公告)号：US20050218490A1

公开(公告)日：2005-10-06

申请号：US11078447

申请日：2005-03-14

申请人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L27/10 ,  H01L21/322 ,  H01L21/52 ,  H01L21/58 ,  H01L23/26 ,  H01L23/31 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US20050199945A1

公开(公告)日：2005-09-15

申请号：US11074064

申请日：2005-03-08

申请人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

发明人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

IPC分类号： H01L21/8247 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/10 ,  H01L29/745 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/1033 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7881

摘要： A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

摘要翻译： 非易失性存储器件包括形成在半导体衬底中的源区和漏区，以及形成在半导体衬底中的源区和漏区之间的沟道区上的绝缘膜。 非易失性存储器件还包括形成在通道区域上方以存储电荷的电介质膜，以及形成在电介质膜上的控制栅极。 通道区域的压缩应力为50MPa以下。

公开(公告)号：US20050029577A1

公开(公告)日：2005-02-10

申请号：US10892553

申请日：2004-07-16

申请人： Teiichirou Nishizaka ,  Kohji Kanamori

发明人： Teiichirou Nishizaka ,  Kohji Kanamori

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/94

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/0491 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7923

摘要： A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the selection gate electrode are included. A channel formed immediately below the selection gate and which constitutes a passage connecting the two diffusion regions has a shape in a top view, including a first path extending in one direction, from one diffusion region, and a second path extending from the end of the first path to the other diffusion region in a direction orthogonal to a first direction.

摘要翻译： 包括半导体存储器件，其包括扩散区域，浮置栅极，第三扩散区域，选择栅极电极和三维地穿过选择栅电极并沿与选择栅电极正交的方向延伸的控制栅电极。 形成在选择栅极正下方的通道，其构成连接两个扩散区域的通道，具有从一个扩散区域向一个扩散区域延伸的包括从一个方向延伸的第一路径和从第二路径延伸的第二路径的俯视图形状 在与第一方向正交的方向上的另一扩散区的第一路径。

公开(公告)号：US20050012172A1

公开(公告)日：2005-01-20

申请号：US10915773

申请日：2004-08-11

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/115

摘要： A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

摘要翻译： 已经公开了一种半导体器件，其包括由可以与堆叠的膜图案（7）自对准的沟槽隔离的存储器单元。 存储单元可以是具有可以比栅极氧化膜（30）薄的有源栅极膜（2）的闪存单元。 有源栅极膜（2）可以位于栅电极（3）下方的中心部分。 栅极氧化膜（30）可以位于栅电极（3）的端部下方。 以这种方式，可以增加沟槽（11）的肩部与栅电极（3）之间的距离。 因此，可以减小沟槽（11）的肩部中的电场集中，并且可以提高存储单元特性。

公开(公告)号：US06426257B1

公开(公告)日：2002-07-30

申请号：US09552226

申请日：2000-04-19

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In a flash memory that has a floating gate, a control gate, and an erase gate that are all mutually insulated, in which data erasing is performed by extracting electrons from the corner edge of the floating gate to the erase gate via an insulation film, the insulation film between the floating gate and the erase gate is formed so as to have a uniform thickness at its corner part.

摘要翻译： 在具有浮动栅极，控制栅极和擦除栅极的闪速存储器中，其全部是相互绝缘的，其中通过经由绝缘膜从浮置栅极的角边缘提取电子到擦除栅极执行数据擦除， 浮栅和擦除栅之间的绝缘膜形成为在其角部具有均匀的厚度。

公开(公告)号：US06339242B2

公开(公告)日：2002-01-15

申请号：US09730312

申请日：2000-12-05

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device has a construction in which a gate dielectric film is formed on the surface of a semiconductor substrate having source regions and drain regions, a plurality of FG (Floating Gates) are formed on the gate dielectric film, an intergate dielectric film is formed on the FG, and CG (Control Gates) are formed on the intergate dielectric film. Mounds are formed on both sides of the FG. An interlayer dielectric film is formed between the gate dielectric film and the intergate dielectric film and covering these mounds. The FG are constituted by upper FG and lower FG, and the upper FG are formed to spread toward the areas where the mounds are formed and cover a portion of the interlayer dielectric film. The gate dielectric film is formed in a shape that does not rise in a direction that is substantially perpendicular to the surface of the semiconductor substrate at least above the upper FG.

摘要翻译： 半导体器件具有在具有源极区域和漏极区域的半导体衬底的表面上形成栅极电介质膜的结构，在栅极电介质膜上形成多个FG（浮动栅极），形成栅极间电介质膜 在栅极电介质膜上形成FG，CG（控制栅）。 在FG的两侧形成土丘。 在栅极电介质膜和隔间绝缘膜之间形成层间绝缘膜，并覆盖这些土堆。 FG由上部FG和下部FG构成，并且上部FG形成为向形成有丘的区域扩展并覆盖层间电介质膜的一部分。 栅极电介质膜形成为至少在上部FG上方在基本上垂直于半导体衬底的表面的方向上不上升的形状。