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    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device
    3.
    发明申请
    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件和非易失性半导体存储器件中的编程方法

    公开(公告)号：US20050185470A1

    公开(公告)日：2005-08-25

    申请号：US11059382

    申请日：2005-02-17

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/3468 ,  G11C16/12

    摘要： A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program pulse to first memory cells while progressively increasing a programming capability of the first program pulse until threshold voltages of the first memory cells become higher than or equal to a first reference voltage. In the second programming mode, the programming circuit applies a second program pulse to second memory cells included in the first memory cells and having threshold voltages lower than a second reference voltage that is higher than the first reference voltage until the threshold voltages of the second memory cells become higher than or equal to the second reference voltage.

    摘要翻译： 存储单元阵列包括多个存储单元，每个存储单元具有控制栅极和浮置栅极。 编程电路以第一编程模式工作，随后是第二编程模式。 在第一编程模式中，编程电路将第一编程脉冲施加到第一存储单元，同时逐渐增加第一编程脉冲的编程能力，直到第一存储单元的阈值电压变为高于或等于第一参考电压。 在第二编程模式中，编程电路将第二编程脉冲施加到包括在第一存储单元中的第二存储单元，并具有低于高于第一参考电压的第二参考电压的阈值电压，直到第二存储器的阈值电压 单元变得高于或等于第二参考电压。

    Method and apparatus for testing defective portion of semiconductor device
    4.
    发明申请
    Method and apparatus for testing defective portion of semiconductor device 有权
    用于测试半导体器件的缺陷部分的方法和装置

    公开(公告)号：US20050218922A1

    公开(公告)日：2005-10-06

    申请号：US11088833

    申请日：2005-03-25

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C16/06 ,  G11C29/00 ,  G11C29/06 ,  H01L21/66 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G01R31/2621

    摘要： An apparatus for testing a defect, includes a semiconductor element. In the semiconductor element, a conductive film is formed on an STI (shallow trench isolation) insulating film, which fills a shallow trench extending into a semiconductor region, through an insulating film in an ordinary state, and the shallow trench is not completely or sufficiently filled with the STI insulating film in a defective state. Also, the apparatus includes a control circuit configured to set a test mode in response to a test mode designation signal, a first voltage applying circuit configured to output a first voltage to the conductive film in the test mode, and a second voltage applying circuit configured to output a second voltage to the semiconductor region in the test mode. The first voltage is higher than the second voltage, and a voltage difference between the first voltage and the second voltage is sufficient to cause breakdown between the conductive film and the semiconductor region in the defective state.

    摘要翻译： 用于测试缺陷的装置包括半导体元件。 在半导体元件中，在通常通过绝缘膜的STI（浅沟槽隔离）绝缘膜上形成导电膜，其通过绝缘膜填充延伸到半导体区域中的浅沟槽，并且浅沟槽不完全或充分 填充有缺陷状态的STI绝缘膜。 此外，该装置包括：控制电路，被配置为响应于测试模式指定信号设置测试模式;第一电压施加电路，被配置为在测试模式下向导电膜输出第一电压;以及第二电压施加电路， 以在测试模式中向半导体区域输出第二电压。 第一电压高于第二电压，并且第一电压和第二电压之间的电压差足以导致在缺陷状态下导电膜和半导体区域之间的击穿。

    Method and apparatus for testing defective portion of semiconductor device
    5.
    发明授权
    Method and apparatus for testing defective portion of semiconductor device 有权
    用于测试半导体器件的缺陷部分的方法和装置

    公开(公告)号：US07138817B2

    公开(公告)日：2006-11-21

    申请号：US11088833

    申请日：2005-03-25

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L23/58

    CPC分类号： G01R31/2621

    摘要： An apparatus for testing a defect, includes a semiconductor element. In the semiconductor element, a conductive film is formed on an STI (shallow trench isolation) insulating film, which fills a shallow trench extending into a semiconductor region, opposing said semiconductor region through an insulating film in an ordinary state, and the shallow trench is not completely or sufficiently filled with the STI insulating film in a defective state. Also, the apparatus includes a control circuit configured to set a test mode in response to a test mode designation signal, a first voltage applying circuit configured to output a first voltage to the conductive film in the test mode, and a second voltage applying circuit configured to output a second voltage to the semiconductor region in the test mode. The first voltage is higher than the second voltage, and a voltage difference between the first voltage and the second voltage is sufficient to cause breakdown between the conductive film and the semiconductor region in the defective state.

    摘要翻译： 用于测试缺陷的装置包括半导体元件。 在半导体元件中，导电膜形成在STI（浅沟槽隔离）绝缘膜上，该绝缘膜填充通过通常的绝缘膜与所述半导体区域相对的半导体区域的浅沟槽，浅沟槽是 不完全或充分地填充有缺陷状态的STI绝缘膜。 此外，该装置包括：控制电路，被配置为响应于测试模式指定信号设置测试模式;第一电压施加电路，被配置为在测试模式下向导电膜输出第一电压;以及第二电压施加电路， 以在测试模式中向半导体区域输出第二电压。 第一电压高于第二电压，并且第一电压和第二电压之间的电压差足以导致在缺陷状态下导电膜和半导体区域之间的击穿。

    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件和非易失性半导体存储器件中的编程方法

    公开(公告)号：US07116581B2

    公开(公告)日：2006-10-03

    申请号：US11059382

    申请日：2005-02-17

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3468 ,  G11C16/12

    摘要： A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program pulse to first memory cells while progressively increasing a programming capability of the first program pulse until threshold voltages of the first memory cells become higher than or equal to a first reference voltage. In the second programming mode, the programming circuit applies a second program pulse to second memory cells included in the first memory cells and having threshold voltages lower than a second reference voltage that is higher than the first reference voltage until the threshold voltages of the second memory cells become higher than or equal to the second reference voltage.

    摘要翻译： 存储单元阵列包括多个存储单元，每个存储单元具有控制栅极和浮置栅极。 编程电路以第一编程模式工作，随后是第二编程模式。 在第一编程模式中，编程电路将第一编程脉冲施加到第一存储单元，同时逐渐增加第一编程脉冲的编程能力，直到第一存储单元的阈值电压变为高于或等于第一参考电压。 在第二编程模式中，编程电路将第二编程脉冲施加到包括在第一存储单元中的第二存储单元，并具有低于高于第一参考电压的第二参考电压的阈值电压，直到第二存储器的阈值电压 单元变得高于或等于第二参考电压。

    Method of fabricating semiconductor memory device
    7.
    发明授权
    Method of fabricating semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US07098104B2

    公开(公告)日：2006-08-29

    申请号：US10822676

    申请日：2004-04-13

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    摘要： A silicon layer doped with an impurity for a floating gate, a protective layer, a silicon nitride layer of a laminated hard mask and a first NSG layer are formed into a desired pattern, on which a second NSG layer is formed and left as a side wall. With the second NSG layer as a mask, the silicon nitride layer is etched. Using the remaining silicon nitride layer as a mask, the silicon layer is etched to form a silicon pattern whose surface is covered with a second protective layer, and the silicon nitride layer is etched out. Accordingly, it is possible to prevent a damage at the surface of the floating gate at the time of forming the floating gate using doped polysilicon.

    摘要翻译： 掺杂有用于浮置栅极，保护层，层叠硬掩模和第一NSG层的氮化硅层的杂质的硅层形成为期望的图案，其上形成有第二NSG层并且作为侧面 壁。 以第二NSG层作为掩模，蚀刻氮化硅层。 使用剩余的氮化硅层作为掩模，蚀刻硅层以形成其表面被第二保护层覆盖的硅图案，并且蚀刻氮化硅层。 因此，可以防止在使用掺杂多晶硅形成浮置栅极时在浮栅的表面处的损坏。

    Light source apparatus, discharge lamp driving method, and projector
    8.
    发明授权
    Light source apparatus, discharge lamp driving method, and projector 有权
    光源装置，放电灯驱动方法和投影仪

    公开(公告)号：US09526157B2

    公开(公告)日：2016-12-20

    申请号：US13549579

    申请日：2012-07-16

    申请人： Junichi Suzuki ,  Satoshi Kito

    发明人： Junichi Suzuki ,  Satoshi Kito

    IPC分类号： H05B41/24 ,  H05B41/36 ,  H05B37/02 ,  G05F1/52 ,  H05B41/292 ,  H05B41/288 ,  G03B21/20

    CPC分类号： H05B41/2928 ,  G03B21/2026 ,  H05B41/2885 ,  Y02B20/202 ,  Y02B20/208

    摘要： A light source apparatus includes a discharge lamp including a light-emitting container having a cavity in which a discharge medium is enclosed, and a pair of electrodes disposed such that respective tip portions thereof oppose each other in the cavity, and a driving unit that supplies a driving current to the pair of electrodes. The driving current is generated by modulating amplitude of alternating current having a frequency not lower than 1 kHz and not higher than 10 GHz, such that a first section and a second section in which the amplitude is smaller than in the first section are alternately repeated.

    摘要翻译： 一种光源装置，包括放电灯，该放电灯包括发光容器，该发光容器具有封闭放电介质的空腔;以及一对电极，其设置成使其各自的前端部分在空腔中相对;以及驱动单元， 到一对电极的驱动电流。 通过调制具有不低于1kHz且不高于10GHz的频率的交变电流的振幅来产生驱动电流，使得其中振幅小于第一部分的第一部分和第二部分交替重复。

    Work system for substrates and working machine
    9.
    发明授权
    Work system for substrates and working machine 有权
    基板和作业机械的工作系统

    公开(公告)号：US09346625B2

    公开(公告)日：2016-05-24

    申请号：US14414928

    申请日：2012-07-17

    申请人： Junichi Suzuki

    发明人： Junichi Suzuki

    IPC分类号： B65G43/10 ,  H05K13/08 ,  B65G37/00 ,  B65G43/00 ,  B65G43/08 ,  H05K13/04 ,  H05K13/00

    CPC分类号： B65G43/10 ,  B65G37/00 ,  B65G43/00 ,  B65G43/08 ,  B65G2811/0673 ,  H05K13/0061 ,  H05K13/04 ,  H05K13/08 ,  H05K13/0817 ,  H05K13/085

    摘要： In a work system for substrates which includes plural working machines conveying circuit substrates through two paths and in which the circuit substrates are conveyed through the two paths from the working machine disposed upstream out of the plural working machines to the working machine disposed downstream, a circuit substrate of which the work result is not good is conveyed to the downstream working machine earlier than the circuit substrate of which the work result is good in a state in which the circuit substrate of which the work result is good and the circuit substrate of which the work result is not good are able to be conveyed to the downstream working machine by the upstream working machine.

    摘要翻译： 在基板的工作系统中，包括通过两条路径输送电路基板的多个工作机械，其中，电路基板从设置在多个加工机械的上游的作业机械的两条路径输送到设置在下游的工作机械， 工作结果不好的基板比工作结果良好的电路基板的状态良好地输送到下游工作机械，其中工作结果良好的电路基板和其工作结果良好的电路基板 工作结果不好，能够通过上游工作机向下游工作机输送。