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253 条记录 (耗时 0.05 秒)

    DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE
    41.
    发明申请
    DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
    双层封装层互连结构

    公开(公告)号：US20080293257A1

    公开(公告)日：2008-11-27

    申请号：US12186923

    申请日：2008-08-06

    申请人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

    发明人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

    摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

    摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。 高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。 每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

    Replacement metal gate processing with reduced interlevel dielectric layer etch rate
    42.
    发明授权
    Replacement metal gate processing with reduced interlevel dielectric layer etch rate 失效
    替代金属栅极处理，具有降低的层间电介质层蚀刻速率

    公开(公告)号：US08546209B1

    公开(公告)日：2013-10-01

    申请号：US13524576

    申请日：2012-06-15

    申请人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66545 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removing at least one layer from the dummy transistor gate structure, wherein the at least one layer comprises a same material as the ILD layer and wherein the GCIB layer has a slower etch rate with respect to the ILD layer.

    摘要翻译： 形成半导体器件结构的方法包括在半导体衬底上形成层间电介质（ILD）层，以及在衬底上形成的虚设晶体管栅极结构; 在浅层气体簇离子束（GCIB）层中注入ILD层的顶部; 以及从所述虚拟晶体管栅极结构去除至少一个层，其中所述至少一个层包含与所述ILD层相同的材料，并且其中所述GCIB层相对于所述ILD层具有较慢的蚀刻速率。

    Electrical Fuse With Metal Line Migration
    43.
    发明申请
    Electrical Fuse With Metal Line Migration 审中-公开
    具有金属线迁移的电气保险丝

    公开(公告)号：US20130071998A1

    公开(公告)日：2013-03-21

    申请号：US13234205

    申请日：2011-09-16

    申请人： Baozhen Li ,  Yan Zun Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Baozhen Li ,  Yan Zun Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/326 ,  H01L21/28 ,  H01L23/52

    CPC分类号： H01L23/5256 ,  H01L21/326 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.

    摘要翻译： 公开了一种电熔丝装置。 电路装置可以包括熔丝装置，第一电路元件和第二电路元件。 熔丝包括具有第一电迁移电阻的第一触点，具有第二电迁移电阻的第二触点和耦合到第一触点和第二触点的金属线，其具有低于 第二次电迁移阻力。 第一电路元件耦合到第一触点，而第二电路元件耦合到第二触点。 保险丝被配置为通过金属线将编程电流从第一触点传导到第二触点。 此外，编程电流使金属线电离远离第二触点，以将第二电路元件与第一电路元件电隔离。

    Hybrid interconnect structure for performance improvement and reliability enhancement
    44.
    发明授权
    Hybrid interconnect structure for performance improvement and reliability enhancement 有权
    混合互连结构，用于性能改进和可靠性提升

    公开(公告)号：US07973409B2

    公开(公告)日：2011-07-05

    申请号：US11625576

    申请日：2007-01-22

    申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

    摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

    STRUCTURE FOR METAL CAP APPLICATIONS
    46.
    发明申请
    STRUCTURE FOR METAL CAP APPLICATIONS 有权
    金属盖应用结构

    公开(公告)号：US20110003473A1

    公开(公告)日：2011-01-06

    申请号：US12881806

    申请日：2010-09-14

    申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

    发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76885 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849

    摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

    摘要翻译： 提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。 此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。