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309 条记录 (耗时 0.03 秒)

    Three-dimensional island pixel photo-sensor
    41.
    发明授权
    Three-dimensional island pixel photo-sensor 有权
    三维岛像素光电传感器

    公开(公告)号：US06720595B2

    公开(公告)日：2004-04-13

    申请号：US09922077

    申请日：2001-08-06

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    IPC分类号： H01L31062

    CPC分类号： H01L27/14634 ,  H01L27/1463 ,  H01L27/14643

    摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

    摘要翻译： 公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。 利用本发明，侧壁垂直于接收入射光的光电二极管的表面。 感光侧壁包括当用光照射时引起电子转移的结区域。 侧壁包围围绕每个岛芯的四个垂直侧壁。 逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

    Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same
    42.
    发明授权
    Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same 有权
    具有SRAM，DRAM和闪速存储器的集成芯片及其制造方法

    公开(公告)号：US06556477B2

    公开(公告)日：2003-04-29

    申请号：US09861788

    申请日：2001-05-21

    申请人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

    IPC分类号： G11C1134

    CPC分类号： H01L27/105 ,  G11C11/005 ,  H01L27/1052

    摘要： A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.

    摘要翻译： 提出了在一个衬底上制造的半导体存储器系统，其包括SRAM器件，DRAM器件和闪存器件。 在一个实施例中，SRAM器件是高电阻负载SRAM器件。 在另一个实施例中，DRAM器件是深沟槽DRAM器件。 还提出了一种用于在具有SRAM器件，DRAM器件和闪存器件的一个衬底上制造存储器系统的方法。

    Integrated redundancy architecture system for an embedded DRAM
    43.
    发明授权
    Integrated redundancy architecture system for an embedded DRAM 有权
    嵌入式DRAM的集成冗余架构系统

    公开(公告)号：US06542973B2

    公开(公告)日：2003-04-01

    申请号：US09898434

    申请日：2001-07-03

    申请人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata ,  Gregory J. Fredeman

    发明人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata ,  Gregory J. Fredeman

    IPC分类号： G06F1200

    CPC分类号： G11C29/846 ,  G06F12/0893

    摘要： An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from a SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed. The integrated redundancy eDRAM architecture system enables data to be sent and received to and from the eDRAM macro system without adding any extra delay to the data flow, thereby protecting data flow pattern integrity.

    摘要翻译： 公开了一种用于具有宽数据带宽和宽内部总线宽度的嵌入式DRAM宏系统的集成冗余eDRAM架构系统，其为eDRAM宏系统的有缺陷的列和行提供列和行冗余。 在eDRAM宏测试模式期间，每个微小区块的有缺陷的列和行的内部生成的列和行地址存储在诸如保险丝库的存储器件中，以便在eDRAM的每个周期期间快速检索信息 操作提供类似SRAM的操作。 列转向电路引导列冗余元件来替换有缺陷的列元素。 根据是否正在执行读取或写入操作，冗余信息是从SRAM熔丝数据存储设备提供的，或者从TAG存储设备提供的。 集成冗余eDRAM架构系统使数据能够从eDRAM宏系统发送和接收数据，而不会对数据流增加任何额外的延迟，从而保护数据流模式的完整性。

    Method for fabricating flash memory device using dual damascene process
    44.
    发明授权
    Method for fabricating flash memory device using dual damascene process 失效
    使用双镶嵌工艺制造闪存器件的方法

    公开(公告)号：US06492227B1

    公开(公告)日：2002-12-10

    申请号：US09624563

    申请日：2000-07-24

    申请人： Li-Kong Wang ,  Louis L. Hsu ,  Wei Hwang

    发明人： Li-Kong Wang ,  Louis L. Hsu ,  Wei Hwang

    IPC分类号： H01L218234

    CPC分类号： H01L21/28273

    摘要： A method is provided for fabricating memory devices on a semiconductor substrate using a dual damascene process. The method includes the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material on surroundings of the at least one dummy gate structure, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate. Support devices may be fabricated on the semiconductor substrate by a single damascene process this is integrated with the processes of fabricating the memory devices, so that top surfaces of the support devices and the memory devices are substantially coplanar.

    摘要翻译： 提供了一种使用双镶嵌工艺在半导体衬底上制造存储器件的方法。 该方法包括以下步骤：在半导体衬底上形成用于至少一个存储器件的至少一个虚拟栅极结构，在至少一个虚拟栅极结构的周围沉积介电材料，蚀刻电介质材料和至少一个虚拟栅极结构 以形成至少一个控制栅极空隙和至少一个浮置栅极空隙，在所述至少一个浮置栅极空隙的底表面上形成栅极电介质层，在至少一个浮置栅极中的栅极介电层上沉积浮置栅极材料 空隙以形成浮置栅极，在浮置栅极上沉积介电层，以及将控制栅极材料沉积在所述至少一个控制栅极中的介电层上以形成控制栅极。 可以通过单个镶嵌工艺在半导体衬底上制造支撑装置，其与制造存储器件的工艺集成，使得支撑装置和存储装置的顶表面基本上共面。

    Self-refresh on-chip voltage generator
    45.
    发明授权
    Self-refresh on-chip voltage generator 失效
    自刷新片上电压发生器

    公开(公告)号：US06411157B1

    公开(公告)日：2002-06-25

    申请号：US09606650

    申请日：2000-06-29

    申请人： Louis L. Hsu ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Li-Kong Wang

    IPC分类号： G05F302

    CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/073

    摘要： A voltage control system and methodology for maintaining internally generated voltage levels in a semiconductor chip. The method comprises the steps of intermittently sampling an internal voltage supply level during a low power or “sleep” mode of operation; comparing the internal voltage supply level against a predetermined voltage reference level; and, activating a voltage supply generator for increasing the internal voltage supply level when the internal voltage supply level falls below the predetermined voltage reference level. The voltage supply generator is subsequently deactivated when the voltage supply level is restored to the predetermined voltage reference level. The sampling cycle may be appropriately tailored according to chip condition, chip temperature, and chip size. In one embodiment, the voltage control system and methodology is implemented in DRAM circuits during a refresh operation. The voltage levels that are suitable for sampling including DRAM band-gap reference voltage, boost wordline line voltage, wordline low voltage, bitline high voltage and bitline equalization voltages.

    摘要翻译： 一种用于维持半导体芯片内部产生的电压电平的电压控制系统和方法。 该方法包括以下步骤：在低功率或“睡眠”操作模式期间间歇地采样内部电压供应电平; 将内部电压供应电平与预定电压参考电平进行比较; 以及当所述内部电压供应电平低于所述预定电压参考电平时激活用于增加所述内部电压供应电平的电压源发生器。 当电压供应电平恢复到预定电压参考电平时，电压发生器随后被去激活。 采样周期可以根据芯片条件，芯片温度和芯片尺寸进行适当调整。 在一个实施例中，电压控制系统和方法在刷新操作期间在DRAM电路中实现。 适用于采样的电压电平，包括DRAM带隙参考电压，升压字线电压，字线低电压，位线高电压和位线均衡电压。

    Content addressable memory having reduced power consumption
    49.
    发明授权
    Content addressable memory having reduced power consumption 有权
    内容可寻址存储器具有降低的功耗

    公开(公告)号：US07216284B2

    公开(公告)日：2007-05-08

    申请号：US10145018

    申请日：2002-05-15

    申请人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

    IPC分类号： G11C29/00

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.

    摘要翻译： 内容可寻址存储器（CAM）。 CAM阵列的数据部分包括字数据存储。 每个字线包括数据部分中的CAM单元（动态或静态）和公共字匹配线。 CAM阵列的纠错（例如，奇偶校验）部分包含每个字线的纠错单元。 每个字线处的误差校正单元连接到纠错匹配线。 纠错匹配线上的匹配可以对相应的数据匹配线进行预充电。 在数据比较中仅包括在纠错匹配行上具有对应匹配的字线上的数据。 预充电功率只需要一个分数（与所使用的误差校正的位长度成反比成正比）的整数组。