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47 条记录 (耗时 0.025 秒)

    Plasma process for organic residue removal from copper
    41.
    发明授权
    Plasma process for organic residue removal from copper 有权
    从铜中去除有机残留物的等离子体工艺

    公开(公告)号：US06342446B1

    公开(公告)日：2002-01-29

    申请号：US09407418

    申请日：1999-09-29

    申请人： Patricia B. Smith ,  Antonio L. P. Rotondaro

    发明人： Patricia B. Smith ,  Antonio L. P. Rotondaro

    IPC分类号： H01L2144

    CPC分类号： H01L21/76838 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76814

    摘要： An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the semiconductor substrate, the conductive structure comprised of an oxygen-sensitive conductor and having an exposed surface; oxidizing a portion of the conductive structure (step 313 of FIG. 1); and subjecting the conductive structure to a plasma which incorporates hydrogen or deuterium (step 315 of FIG. 1).

    摘要翻译： 本发明的一个实施例是一种制造形成在半导体晶片上的电子器件的方法，该方法包括以下步骤：在半导体衬底上形成导电结构，该导电结构由氧敏导体组成并具有暴露的 表面; 氧化导电结构的一部分（图1的步骤313）; 并对导电结构进行掺入氢或氘的等离子体（图1的步骤315）。

    BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE
    43.
    发明申请
    BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE 有权
    具有降低PARASITIC电容的身体接触晶体管

    公开(公告)号：US20110163382A1

    公开(公告)日：2011-07-07

    申请号：US12652364

    申请日：2010-01-05

    申请人： Antonio L. P. Rotondaro

    发明人： Antonio L. P. Rotondaro

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

    摘要： A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region.

    摘要翻译： 提供了一种接触绝缘体上半导体（SOI）金属栅极的晶体管，其具有降低的寄生栅极电容，其中栅极堆叠的金属部分在主体接触区域上被去除，并且形成接触的含硅材料 在SOI衬底的体接触区域中的栅极电介质。 这导致在身体接触区域上的有效栅极电介质厚度增加大于5埃（Å）。 这导致在身体接触区域的较低的寄生电容。

    Semiconductor device manufactured using a laminated stress layer
    44.
    发明授权
    Semiconductor device manufactured using a laminated stress layer 有权
    使用层压应力层制造的半导体器件

    公开(公告)号：US07611939B2

    公开(公告)日：2009-11-03

    申请号：US11745044

    申请日：2007-05-07

    申请人： Manoj Mehrotra ,  Antonio L. P. Rotondaro ,  Puneet Kohli

    发明人： Manoj Mehrotra ,  Antonio L. P. Rotondaro ,  Puneet Kohli

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76828 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

    摘要翻译： 提出了形成半导体器件的方法。 该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。 在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底之上形成层压应力层。 层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。 在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

    Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology
    45.
    发明授权
    Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology 有权
    具有低介电常数材料的封装间隔物，以减少CMOS技术中栅极和漏极之间的寄生电容

    公开(公告)号：US07033897B2

    公开(公告)日：2006-04-25

    申请号：US10692388

    申请日：2003-10-23

    申请人： Yuanning Chen ,  Antonio L. P. Rotondaro ,  Karen H. Kirmse

    发明人： Yuanning Chen ,  Antonio L. P. Rotondaro ,  Karen H. Kirmse

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

    摘要： The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.

    摘要翻译： 本发明涉及以减轻寄生电容的方式形成晶体管，从而促进了切换速度的提高。 更具体地，形成在与导电栅极结构相邻的半导体衬底上的侧壁间隔物包括具有低介电常数（低k）的材料，以减轻栅极结构，侧壁间隔物和形成在半导体衬底内的导电漏极之间的寄生电容 。 低k侧壁间隔物被封装在对蚀刻剂有选择性的氮化物材料内，使得间隔物在随后的处理期间不改变。 间隔物因此保持其形状并且仍然有效地将掺杂剂引导到衬底内的期望位置。