Damascene process of RRAM top electrodes
    46.
    发明授权
    Damascene process of RRAM top electrodes 有权
    RRAM顶电极的镶嵌工艺

    公开(公告)号:US09425391B1

    公开(公告)日:2016-08-23

    申请号:US14638189

    申请日:2015-03-04

    Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

    Abstract translation: 提供了一种用于制造存储器的方法。 在层间导体阵列之上形成绝缘层,并蚀刻以形成对应于阵列中的第一层间导体的第一开口,其中蚀刻停止在第一层间导体的第一顶表面处。 金属氧化物层形成在第一顶表面上。 第一层阻挡材料与第一开口的金属氧化物层和表面共形并与其接触。 随后,绝缘层被蚀刻以限定对应于阵列中的第二层间导体的第二开口,其中蚀刻停止在第二层间导体的第二顶表面处。 第二层阻挡材料与第一开口中的第一阻隔材料层共形并与其接触。 第一个开口填充有导电材料。

    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    47.
    发明申请
    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号:US20160240776A1

    公开(公告)日:2016-08-18

    申请号:US14623654

    申请日:2015-02-17

    Abstract: A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is formed in the recess and has a top surface exposed from an opening of the recess. The spacer covers on a portion of the top surface, so as to define a contact area on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and electrically connected to the memory layer.

    Abstract translation: 存储器件包括衬底,第一电极层,间隔物,存储层和第二电极层。 基板具有凹部。 第一电极层形成在凹部中并且具有从凹部的开口露出的顶表面。 间隔件覆盖在顶表面的一部分上,以便限定顶表面上的接触区域。 存储层形成在接触区域上。 第二电极层形成在存储层上并与存储层电连接。

    RESISTIVE MEMORY DEVICE WITH RING-SHAPED METAL OXIDE ON TOP SURFACES OF RING-SHAPED METAL LAYER AND BARRIER LAYER
    48.
    发明申请
    RESISTIVE MEMORY DEVICE WITH RING-SHAPED METAL OXIDE ON TOP SURFACES OF RING-SHAPED METAL LAYER AND BARRIER LAYER 有权
    具有环形金属氧化物的环形存储器件在环形金属层和障碍层的顶表面上

    公开(公告)号:US20160225983A1

    公开(公告)日:2016-08-04

    申请号:US14603390

    申请日:2015-01-23

    CPC classification number: H01L45/146 H01L45/04 H01L45/124 H01L45/1633

    Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

    Abstract translation: 提供了一种电阻式存储器件,包括底部电极,形成在底部电极上的通孔的图案化电介质层,形成在通孔的侧壁和底部表面的阻挡层作为衬垫,形成在环形金属层 侧壁和阻挡层的底表面,以及形成在环形金属层的顶表面上的环形金属氧化物。

    Ternary content addressable memory and decision generation method for the same

    公开(公告)号:US12211550B2

    公开(公告)日:2025-01-28

    申请号:US18420874

    申请日:2024-01-24

    Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

    Memory cell and memory device thereof

    公开(公告)号:US12190941B2

    公开(公告)日:2025-01-07

    申请号:US18147015

    申请日:2022-12-28

    Abstract: A memory cell and a memory device are provided. The memory cell comprises: a write transistor; and a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data; wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable.

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