公开(公告)号：US20140160849A1

公开(公告)日：2014-06-12

申请号：US14176794

申请日：2014-02-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Ti Wen Chen

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C29/785

Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.

Abstract translation: 不管存储在数据存储单元上的数据值如何，都不允许对数据存储单元进行所有读操作。 例如，通过一串数据存储单元和一个或多个选择行存储单元不允许当前流。 存储在字符串中的第一选择行存储单元中的特定选择值，例如耦合到接地选择线或字符串选择行，确定字符串是启用还是禁用。

公开(公告)号：US20230402085A1

公开(公告)日：2023-12-14

申请号：US17838921

申请日：2022-06-13

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung

IPC: G11C11/406 ,  G11C11/4096 ,  H03K19/20

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4096 ,  H03K19/20

Abstract: Methods, devices, and systems for managing data refresh for semiconductor devices are provided. In one aspect, a semiconductor device includes a memory cell array having a plurality of blocks each including multiple pages and one or more integrated circuits coupled to the memory cell array. The one or more integrated circuits are configured to: read specific data from a page of a block in the memory cell array, perform a logic operation on the specific data in the page to obtain a logic operation result, count a number of bits having a specific value among the logic operation result, determine whether the number of bits is within a data refresh criterion for the page, and in response to determining that the number of bits is outside of the data refresh criterion, generate a data refresh warning message for the page in the block.

公开(公告)号：US11742004B2

公开(公告)日：2023-08-29

申请号：US17535021

申请日：2021-11-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Nai-Ping Kuo ,  Chien-Hsin Liu

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1069 ,  G11C7/1096

Abstract: A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.

公开(公告)号：US11461025B2

公开(公告)日：2022-10-04

申请号：US17089972

申请日：2020-11-05

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  E-Yuan Chang

IPC: G06F3/06

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

公开(公告)号：US11087858B1

公开(公告)日：2021-08-10

申请号：US16938500

申请日：2020-07-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Lien Su

IPC: G11C16/16 ,  G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C29/18

Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

公开(公告)号：US11048649B2

公开(公告)日：2021-06-29

申请号：US16544055

申请日：2019-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung

IPC: G06F13/16 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device such as a page mode NAND flash including a page buffer, and an input/output interface for I/O data units having an I/O width less than the page width supports continuous page read with non-sequential addresses. A controller controls a continuous page read operation to output a stream of pages at the I/O interface. The continuous read operation includes responding to a series of commands to output a continuous stream of pages. The series of commands including a first command and a plurality of intra-stream commands received before completing output of a preceding page in the stream. The first command includes an address to initiate the continuous page read operation, and at least one intra-stream command in the plurality of intra-stream commands includes a non-sequential address to provide the non-sequential page in the stream of pages.

公开(公告)号：US10290364B2

公开(公告)日：2019-05-14

申请号：US14849412

申请日：2015-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chi Lo ,  Chun-Hsiung Hung

IPC: G11C29/04 ,  G11C29/00

Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

公开(公告)号：US20180005699A1

公开(公告)日：2018-01-04

申请号：US15705001

申请日：2017-09-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Shin-Jang Shen ,  Wei-Jen Chen

IPC: G11C16/14 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/08

Abstract: A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

公开(公告)号：US08982628B2

公开(公告)日：2015-03-17

申请号：US14176794

申请日：2014-02-10

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Ti Wen Chen

IPC: G11C16/04 ,  G11C16/26 ,  G11C29/00

CPC classification number: G11C16/26 ,  G11C29/785

Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.

Abstract translation: 不管存储在数据存储单元上的数据值如何，都不允许对数据存储单元进行所有读操作。 例如，通过一串数据存储单元和一个或多个选择行存储单元不允许当前流。 存储在字符串中的第一选择行存储单元中的特定选择值，例如耦合到接地选择线或字符串选择行，确定字符串是启用还是禁用。

公开(公告)号：US08982622B2

公开(公告)日：2015-03-17

申请号：US14066450

申请日：2013-10-29

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung

IPC: G11C16/04 ,  H01L27/115 ,  H01L23/522

CPC classification number: G11C16/04 ,  G11C16/0483 ,  H01L23/5225 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.

Abstract translation: 存储器件包括具有多个电平的存储器单元块。 每个级别包括在块的第一和第二端之间沿第一方向延伸的存储器单元条。 在第一端的每个级别处的第一位线结构耦合到从第一端延伸的第一串存储器单元。 在第二端的每个级别处的第二位线结构耦合到从所述第二端延伸的第二存储单元串。 位线对在第一个方向上延伸，每个包括奇数和偶数位线。 奇偶位线连接器将奇数位和偶数位线分别连接到第二和第一位线结构。 一系列位线对的每个位线由相邻位线对的位线分开。