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    Hardware clock with built-in accuracy check
    42.
    发明授权
    Hardware clock with built-in accuracy check 有权

    公开(公告)号：US11588609B2

    公开(公告)日：2023-02-21

    申请号：US17148605

    申请日：2021-01-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

    IPC: H04W40/20 ,  H04L7/00

    Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

    Application acceleration
    43.
    发明申请
    Application acceleration 有权

    公开(公告)号：US20230012939A1

    公开(公告)日：2023-01-19

    申请号：US17898496

    申请日：2022-08-30

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

    IPC: H04N19/42 ,  H04N19/119 ,  H04N19/176 ,  H04N19/105 ,  H04N19/132

    Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each block of the second plurality of blocks, to produce a score of result blocks based on similarity of each block in each frame to be encoded to every block of the reference frame, an AC energy coefficient, and a displacement vector. Related apparatus and methods are also provided.

    Synthesized clock synchronization between network devices
    47.
    发明申请
    Synthesized clock synchronization between network devices 有权

    公开(公告)号：US20220173741A1

    公开(公告)日：2022-06-02

    申请号：US17670540

    申请日：2022-02-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

    IPC: H03L7/08 ,  G06F1/12 ,  H04L7/033 ,  H03L7/099

    Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

    Packet scheduling system with desired physical transmission time for packets
    48.
    发明授权
    Packet scheduling system with desired physical transmission time for packets 有权

    公开(公告)号：US11336383B2

    公开(公告)日：2022-05-17

    申请号：US16910193

    申请日：2020-06-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ran Ravid ,  Guy Lederman

    IPC: H04J3/06 ,  H04L12/46 ,  H04L43/0852 ,  H04L69/22

    Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.

    Direct Packet Placement
    49.
    发明申请
    Direct Packet Placement 有权

    公开(公告)号：US20220086105A1

    公开(公告)日：2022-03-17

    申请号：US17535608

    申请日：2021-11-25

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis

    IPC: H04L12/939 ,  H04L12/861 ,  H04W28/04 ,  H04L29/06 ,  H04L12/879

    Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

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