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公开(公告)号：US20220164108A1
公开(公告)日：2022-05-26
申请号：US17105000
申请日：2020-11-25
Applicant: Micron Technology, Inc.
Inventor： Donald Martin Morgan , Alan J. Wilson
IPC: G06F3/06
Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.
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公开(公告)号：US11334458B2
公开(公告)日：2022-05-17
申请号：US17005027
申请日：2020-08-27
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald Martin Morgan
Abstract: Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.
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公开(公告)号：US10600496B1
公开(公告)日：2020-03-24
申请号：US16164156
申请日：2018-10-18
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , Alan J. Wilson
Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
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公开(公告)号：US20150287480A1
公开(公告)日：2015-10-08
申请号：US14246589
申请日：2014-04-07
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Jeffrey Wright
IPC: G11C29/00 , G11C17/18 , G11C17/16 , G11C11/408 , G11C11/418
CPC classification number: G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
Abstract translation: 公开了软包装修复的装置和方法。 一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。 匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的缺陷地址数据相匹配的匹配信号。 解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配 。 存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。
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公开(公告)号：US20240370176A1
公开(公告)日：2024-11-07
申请号：US18653300
申请日：2024-05-02
Applicant: Micron Technology, Inc.
Inventor： Bryan D. Kerstetter , Alan J. Wilson , Donald M. Morgan
IPC: G06F3/06
Abstract: Systems, methods, and apparatuses are provided for wear leveling repair in a memory device. A host is configured to issue a wear leveling command and a repair request to a memory device configured to check source data in a memory of the memory device for errors in response to receiving the wear leveling command from the host, transfer source data in the memory of the memory device to a target page, and repair a source page if the source data includes an error. The memory device is further configured to set a new repair match if a wear leveling repair element was not consumed after receiving the repair request and flush a previous repair match before setting the new repair match if the wear leveling repair element was consumed and a physical address of an incoming repair request is associated with the wear leveling repair element.
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Patent Agency Ranking
公开(公告)号：US12086449B1
公开(公告)日：2024-09-10
申请号：US17983213
申请日：2022-11-08
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
CPC classification number: G06F3/0647 , G06F3/0616 , G06F3/0659 , G06F3/0673 , G06F12/10 , G06F2212/657
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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公开(公告)号：US20230350574A1
公开(公告)日：2023-11-02
申请号：US17731100
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F3/0676
Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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公开(公告)号：US11669447B2
公开(公告)日：2023-06-06
申请号：US17488190
申请日：2021-09-28
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , Alan J. Wilson
CPC classification number: G06F12/0692 , G11C11/5628 , G11C29/50 , G11C29/789 , G06F2212/1016
Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.
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公开(公告)号：US20230116534A1
公开(公告)日：2023-04-13
申请号：US17450582
申请日：2021-10-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Donald M. Morgan , Alan J. Wilson , Bryan D. Kerstetter , John D. Porter
IPC: G11C29/00
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.
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公开(公告)号：US11507296B2
公开(公告)日：2022-11-22
申请号：US17197733
申请日：2021-03-10
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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