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41.发明申请公开(公告)号：US20160204343A1
公开(公告)日：2016-07-14
申请号：US14594038
申请日：2015-01-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Gotti , F. Daniel Gealy , Innocenzo Tortorelli , Enrico Varesi
CPC classification number: H01L45/06 , H01L27/224 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1666 , H01L45/1675 , H01L2924/0002 , H01L2924/00
Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.
Abstract translation: 公开的技术大体上涉及集成电路，更具体地说，涉及形成包括钨和碳的金属线（诸如用于存储器阵列的导线）的结构和形成方法。 在一个方面，存储器件包括沿第一方向延伸的下导电线和沿第二方向延伸并与下导电线交叉的上导电线，其中上导线和下导线中的至少一个包括钨和碳。 存储器件还包括插入在上导电线和下导电线之间的交叉点处的存储单元堆叠。 所述存储单元堆叠包括位于所述下导电线上的第一有源元件和所述第一有源元件上的第二有源元件，其中所述第一和第二有源元件中的一个包括存储元件，并且所述第一和第二有源元件中的另一个包括 选择器元件 存储单元堆叠还包括插入在上导电线和下导电线中的至少一个以及第一和第二有源元件的更靠近的电极之间的电极。
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公开(公告)号：US20160104837A1
公开(公告)日：2016-04-14
申请号：US14972152
申请日：2015-12-17
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Andrea Gotti
CPC classification number: H01L45/124 , H01L21/28 , H01L21/3213 , H01L27/1052 , H01L27/222 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
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公开(公告)号：US12213325B2
公开(公告)日：2025-01-28
申请号：US17499709
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Gotti , Pavan Reddy K. Aella
Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
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公开(公告)号：US12205641B2
公开(公告)日：2025-01-21
申请号：US17834702
申请日：2022-06-07
Applicant: Micron Technology, Inc.
Inventor： Nicola Ciocchini , Andrea Gotti
Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.
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45.发明公开公开(公告)号：US20240268093A1
公开(公告)日：2024-08-08
申请号：US18435212
申请日：2024-02-07
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Jieun Lee , Andrea Gotti , Kai Yen Lo , David McShannon , Daniel Rave , Silvia Borsari , Hsiao Wei Liu
IPC: H10B12/00
CPC classification number: H10B12/033 , H10B12/315
Abstract: A method used in forming an array of capacitors comprises forming a stack comprising sacrificial material and insulative material that is between a top and a bottom of the sacrificial material. The insulative material at least predominately comprises at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride. Horizontally-spaced openings are formed partially through the sacrificial material. A lining is deposited within the horizontally-spaced openings and directly above the sacrificial material. After depositing the lining, the horizontally-spaced openings are extended through remaining of the sacrificial material. The extended horizontally-spaced openings extend through the insulative material. The insulative material with extended horizontally-spaced openings there-through comprises an insulative horizontal lattice. First capacitor electrodes are formed that are individually within individual of the extended horizontally-spaced openings laterally over the lining that is in the extended horizontally-spaced openings. The sacrificial material is removed and forms a capacitor insulator over the first capacitor electrodes and the insulative horizontal lattice. Second-capacitor-electrode material is formed over the capacitor insulator. Structure independent of method is disclosed
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Patent Agency Ranking
公开(公告)号：US20230343815A1
公开(公告)日：2023-10-26
申请号：US17726965
申请日：2022-04-22
Applicant: Micron Technology, Inc.
Inventor： Ryan L. Meyer , Vinay Nair , Andrea Gotti , Kevin Shea , Kyle R. Knori
IPC: H01L49/02 , H01L27/108
CPC classification number: H01L28/60 , H01L27/1085
Abstract: Methods, apparatuses, and systems related to depositing a storage node material are described. An example method includes forming a semiconductor structure including a support structure having a first silicate material over a bottom nitride material, a first nitride material over the first silicate material, a second silicate material over the first nitride material, and a second nitride material over the second silicate material. The method further includes removing portions of the second nitride material. The method further includes depositing a third silicate material over the second nitride material and a portion of the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing a storage node material within the opening.
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公开(公告)号：US11641788B2
公开(公告)日：2023-05-02
申请号：US17116559
申请日：2020-12-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Gotti , Dale W. Collins , Fabio Pellizzer
Abstract: Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.
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公开(公告)号：US20220301623A1
公开(公告)日：2022-09-22
申请号：US17834702
申请日：2022-06-07
Applicant: Micron Technology, Inc.
Inventor： Nicola Ciocchini , Andrea Gotti
Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.
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公开(公告)号：US20220181549A1
公开(公告)日：2022-06-09
申请号：US17116559
申请日：2020-12-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Gotti , Dale W. Collins , Fabio Pellizzer
Abstract: Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.
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50.发明授权公开(公告)号：US11081644B2
公开(公告)日：2021-08-03
申请号：US16045550
申请日：2018-07-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Swapnil A. Lengade , John M. Meldrim , Andrea Gotti
Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.
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