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    Memory having internal processors and methods of controlling memory access
    42.
    发明授权
    Memory having internal processors and methods of controlling memory access 有权
    具有内部处理器的内存和控制内存访问的方法

    公开(公告)号：US09164698B2

    公开(公告)日：2015-10-20

    申请号：US14269873

    申请日：2014-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Robert M. Walker ,  Dan Skinner ,  J. Thomas Pawlowski

    IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

    Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.

    Abstract translation: 提供具有内部处理器的记忆和在这种存储器内的数据通信方法。 一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。 取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。 提取单元可以基于银行的可用性来执行命令。 在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。 在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器来等待存储体可用。

    Memory system and method using ECC with flag bit to identify modified data
    43.
    发明授权
    Memory system and method using ECC with flag bit to identify modified data 有权
    使用带有标志位的ECC的存储器系统和方法来识别修改的数据

    公开(公告)号：US08880974B2

    公开(公告)日：2014-11-04

    申请号：US14060304

    申请日：2013-10-22

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski ,  John F. Schreck

    IPC: H03M13/00 ,  G06F11/10 ,  G11C7/10 ,  H03M13/15 ,  G11C11/406 ,  G11C29/52 ,  G11C29/04

    CPC classification number: H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

    Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

    Abstract translation: DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

    MULTI-PORT MEMORY AND OPERATION
    44.
    发明申请
    MULTI-PORT MEMORY AND OPERATION 有权
    多端口存储器和操作

    公开(公告)号：US20140289482A1

    公开(公告)日：2014-09-25

    申请号：US14299237

    申请日：2014-06-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dan Skinner ,  J. Thomas Pawlowski

    IPC: G06F13/16 ,  G11C7/10

    CPC classification number: G06F13/1631 ,  G06F13/16 ,  G06F13/1636 ,  G11C7/1075 ,  G11C8/16 ,  Y02D10/14

    Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

    Abstract translation: 具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。 这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

    PATTERN-RECOGNITION PROCESSOR WITH MATCHING-DATA REPORTING MODULE
    45.
    发明申请
    PATTERN-RECOGNITION PROCESSOR WITH MATCHING-DATA REPORTING MODULE 有权
    具有匹配数据报告模块的模式识别处理器

    公开(公告)号：US20140244564A1

    公开(公告)日：2014-08-28

    申请号：US14269853

    申请日：2014-05-05

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06N5/02

    CPC classification number: G06N5/025 ,  G06F7/02 ,  G06F2207/025 ,  G06K9/62

    Abstract: Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied.

    Abstract translation: 公开了方法和装置，其中包括模式识别处理器的装置。 模式识别处理器可以包括匹配数据报告模块，其可以具有缓冲器和匹配事件表。 缓冲器可以耦合到数据流并且被配置为存储数据流的至少一部分，并且匹配事件表可以被配置为存储指示与满足搜索条件的开始相对应的缓冲器位置的数据。

    MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA
    46.
    发明申请
    MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA 有权
    使用ECC与标记位来识别修改的数据的存储器系统和方法

    公开(公告)号：US20140047305A1

    公开(公告)日：2014-02-13

    申请号：US14060304

    申请日：2013-10-22

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski ,  John F. Schreck

    IPC: H03M13/15

    CPC classification number: H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

    Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

    Abstract translation: DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

    Progressive length error control code
    47.
    发明授权
    Progressive length error control code 有权

    公开(公告)号：US11256570B2

    公开(公告)日：2022-02-22

    申请号：US17075424

    申请日：2020-10-20

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

    BUSES FOR PATTERN-RECOGNITION PROCESSORS
    50.
    发明申请
    BUSES FOR PATTERN-RECOGNITION PROCESSORS 审中-公开

    公开(公告)号：US20190147278A1

    公开(公告)日：2019-05-16

    申请号：US16249682

    申请日：2019-01-16

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06K9/00

    Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

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