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    METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION
    41.
    发明申请
    METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION 审中-公开

    公开(公告)号：US20190272861A1

    公开(公告)日：2019-09-05

    申请号：US16416425

    申请日：2019-05-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Debra Bell ,  Kallol Mazumder

    IPC: G11C7/22 ,  G06F9/30 ,  G11C7/10

    Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

    Data output for high frequency domain
    44.
    发明授权
    Data output for high frequency domain 有权

    公开(公告)号：US10157648B1

    公开(公告)日：2018-12-18

    申请号：US15652986

    申请日：2017-07-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder ,  Myung-Ho Bae

    IPC: G11C7/10 ,  G11C7/22

    Abstract: A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

    Memory device clock swapping
    45.
    发明授权
    Memory device clock swapping 有权

    公开(公告)号：US12189414B2

    公开(公告)日：2025-01-07

    申请号：US17897957

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  Scott E. Smith

    IPC: G06F1/08 ,  G06F1/10

    Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.

    APPARATUS OPERATING IN GEARDOWN MODE
    47.
    发明公开
    APPARATUS OPERATING IN GEARDOWN MODE 审中-公开

    公开(公告)号：US20240321336A1

    公开(公告)日：2024-09-26

    申请号：US18583267

    申请日：2024-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Navya Sri Sreeram ,  Kallol Mazumder

    IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4076

    CPC classification number: G11C11/40615 ,  G11C11/4072 ,  G11C11/4076

    Abstract: Methods, apparatuses, and systems related to an apparatus implementing a geardown mode in a parallel pipeline configuration. The apparatus can include mechanisms to manage signal timing across multiple data processing pipelines for different communication speeds. While operating in a geardown mode, the apparatus can capture a sync pulse in two or more data pipelines. The apparatus can identify the pipeline that first captured the sync pulse and suppress the operation of the other pipelines.

    QED SHIFTER FOR A MEMORY DEVICE
    48.
    发明申请
    QED SHIFTER FOR A MEMORY DEVICE 有权

    公开(公告)号：US20230065930A1

    公开(公告)日：2023-03-02

    申请号：US17459722

    申请日：2021-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder

    IPC: G11C11/4076

    Abstract: A memory device includes a command interface configured to receive a command from a host device. The memory device also includes a command shifter configured to receive the command. The command shifter includes a plurality of stages coupled in series and configured to delay the command. The command shifter comprises selection circuitry configured to receive the command and to select an insertion stage of the plurality of stages for the command. The selection circuitry is configured to select the insertion stage as a location to insert the command. The selected insertion stage is selected to control a duration of delay in the command shifter. The selection of the insertion stage is based at least in part on a path delay between a clock and a data pin of the memory device.

    Shared command shifter systems and methods
    50.
    发明授权
    Shared command shifter systems and methods 有权

    公开(公告)号：US11574661B1

    公开(公告)日：2023-02-07

    申请号：US17501812

    申请日：2021-10-14

    Applicant: Micron Technology, inc.

    Inventor： Kallol Mazumder ,  Navya Sri Sreeram

    IPC: G11C7/10

    Abstract: The systems and methods described herein involve a device that may receive a plurality of commands and generate a common command indicative of matching data signals between each of the plurality of commands. The device may include a first latch that receives a shifted flag and outputs a shifted command in response to a first enable signal. The device may include shifters, where a first shifter may receive the common command, and a last shifter may couple to the first latch. The last shifter may receive a shifter common command and may generate the first enable signal using the shifted common command.

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