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    SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS
    41.
    发明申请
    SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20210141943A1

    公开(公告)日：2021-05-13

    申请号：US16677286

    申请日：2019-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Brenton P. Van Leeuwen ,  Nathaniel J. Meier

    IPC: G06F21/79 ,  G06F21/81 ,  H04L9/06

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

    MEMORY WITH AUTOMATIC BACKGROUND PRECONDITION UPON POWERUP
    42.
    发明申请
    MEMORY WITH AUTOMATIC BACKGROUND PRECONDITION UPON POWERUP 有权

    公开(公告)号：US20210064271A1

    公开(公告)日：2021-03-04

    申请号：US16553859

    申请日：2019-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

    IPC: G06F3/06 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4091 ,  G11C11/4072

    Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.

    APPARATUSES AND METHODS FOR TRACKING VICTIM ROWS
    43.
    发明申请
    APPARATUSES AND METHODS FOR TRACKING VICTIM ROWS 审中-公开

    公开(公告)号：US20200381040A1

    公开(公告)日：2020-12-03

    申请号：US16428625

    申请日：2019-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

    IPC: G11C11/406 ,  G11C11/408

    Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

    Dynamic Address Scramble
    45.
    发明公开
    Dynamic Address Scramble 审中-公开

    公开(公告)号：US20240071464A1

    公开(公告)日：2024-02-29

    申请号：US17823450

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Erik T. Barmon ,  Yang Lu ,  Nathaniel J. Meier ,  Kang-Yong Kim

    IPC: G11C11/408 ,  G11C7/24 ,  G11C29/18 ,  G11C29/56

    CPC classification number: G11C11/408 ,  G11C7/24 ,  G11C29/18 ,  G11C29/56004

    Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

    MEMORY WITH PARTIAL ARRAY DENSITY SECURITY, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
    46.
    发明公开
    MEMORY WITH PARTIAL ARRAY DENSITY SECURITY, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS 审中-公开

    公开(公告)号：US20240038290A1

    公开(公告)日：2024-02-01

    申请号：US17877296

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Shore ,  Nathaniel J. Meier

    IPC: G11C11/4078 ,  G11C11/406

    CPC classification number: G11C11/4078 ,  G11C11/40611

    Abstract: Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.

    Illegal operation reaction at a memory device
    47.
    发明授权
    Illegal operation reaction at a memory device 有权

    公开(公告)号：US11886745B2

    公开(公告)日：2024-01-30

    申请号：US17660938

    申请日：2022-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Nathaniel J. Meier

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for illegal operation reaction are described. A memory device may receive one or more commands to perform one or more respective access operations on an array of memory cells. A first circuit of the memory device may determine that the one or more commands would violate one or more thresholds associated with operation of the memory device, such as a timing threshold. In some cases, the first circuit may compare the one or more commands to the one or more patterns of commands stored at the memory device. A second circuit of the memory device may erase one or more memory cells of the memory device based on determining that the one or more thresholds associated with operation of the memory device would be violated, based on comparing the set of commands to the one or more patterns, or a combination thereof.

    SEMICONDUCTOR DEVICE WITH SELF-LOCK SECURITY AND ASSOCIATED METHODS AND SYSTEMS
    49.
    发明申请
    SEMICONDUCTOR DEVICE WITH SELF-LOCK SECURITY AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20230073070A1

    公开(公告)日：2023-03-09

    申请号：US17982403

    申请日：2022-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Nathaniel J. Meier ,  Brenton P. Van Leeuwen

    IPC: G06F21/79

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which self-lock security may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a predefined event associated with the memory device operation. The predefined event may include an operating parameter of the memory device, one or more commands directed to the memory device, or both. The memory device may monitor the predefined event and determine that the predefined event satisfies a threshold. The threshold may be related to a time elapsed since the predefined event has occurred or a certain pattern in the one or more commands. Subsequently, the memory device may disable a circuit configured to access the fuse array based on the determination such that an access to the fuse array is no longer allowed.

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