公开(公告)号：US10418085B2

公开(公告)日：2019-09-17

申请号：US15655675

申请日：2017-07-20

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

公开(公告)号：US10366740B1

公开(公告)日：2019-07-30

申请号：US16234319

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/4097

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US12131769B2

公开(公告)日：2024-10-29

申请号：US17886217

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C11/408

CPC classification number: G11C11/4085

Abstract: A boost circuit is used to provide boosting voltage to a common boost node of a plurality of sub-word line drivers in memory systems and devices. The boost circuit includes a Metal Insulator Metal Capacitor. By using the boost circuit, the plurality of sub-word line drivers are configured to output a certain voltage to local word lines without using high DC generators to generate high voltages (4.2 volts or more). The area of the semiconductor substrate used for fabricating the sub-word line drivers is reduced, and thus reduce the cost or increasing the capacity of the memory devices.

公开(公告)号：US12080336B2

公开(公告)日：2024-09-03

申请号：US17662198

申请日：2022-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jiyun Li ,  Christopher J. Kawamura ,  Tae H. Kim

IPC: G11C11/4091 ,  H03F3/45

CPC classification number: G11C11/4091 ,  H03F3/45264

Abstract: Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

公开(公告)号：US20230148359A1

公开(公告)日：2023-05-11

申请号：US18048738

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/221

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

公开(公告)号：US11587607B2

公开(公告)日：2023-02-21

申请号：US17697483

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Brenton P. Van Leeuwen

IPC: G11C11/408 ,  G11C11/22

Abstract: Methods, systems, and devices for driving word lines using sub word line drivers are described. A memory array may include a plurality of sub-arrays arranged with gaps in between. Word lines may be arranged across multiple sub-arrays and drive access transistors that are used to selectively access rows (e.g., rows of memory cells) within the sub-arrays. In some examples, signals applied to selection devices driving the word lines may be over-driven for a duration at or near the desired transitions of the word line, and some signals may be driven to a relatively high level for a duration around the high and low transitions of a global row line. Whether a signal is over driven or driven to a relatively high level may depend on the type or types of transistors used in each word line driver.

公开(公告)号：US11501815B2

公开(公告)日：2022-11-15

申请号：US17171873

申请日：2021-02-09

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim ,  Scott James Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

公开(公告)号：US20220254388A1

公开(公告)日：2022-08-11

申请号：US17172257

申请日：2021-02-10

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Beau D. Barry ,  Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/30 ,  G11C16/32

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

公开(公告)号：US11176987B2

公开(公告)日：2021-11-16

申请号：US17114404

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4076

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

公开(公告)号：US11120847B2

公开(公告)日：2021-09-14

申请号：US16747824

申请日：2020-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C8/10 ,  G11C7/12 ,  G11C11/4074

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.