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    APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES
    41.
    发明公开
    APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240063188A1

    公开(公告)日：2024-02-22

    申请号：US18499087

    申请日：2023-10-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: H01L25/065 ,  H01L25/18

    CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

    Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

    Multiple concurrent modulation schemes in a memory system
    44.
    发明授权
    Multiple concurrent modulation schemes in a memory system 有权

    公开(公告)号：US11610613B2

    公开(公告)日：2023-03-21

    申请号：US17212708

    申请日：2021-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

    IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

    Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

    Memory subsystem register clock driver clock teeing
    45.
    发明授权
    Memory subsystem register clock driver clock teeing 有权

    公开(公告)号：US11468931B2

    公开(公告)日：2022-10-11

    申请号：US17360964

    申请日：2021-06-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

    Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

    Equalization for Pulse-Amplitude Modulation
    48.
    发明申请
    Equalization for Pulse-Amplitude Modulation 有权

    公开(公告)号：US20220209998A1

    公开(公告)日：2022-06-30

    申请号：US17562588

    申请日：2021-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: H04L25/03 ,  H04L25/49

    Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

    METHOD TO VERTICALLY ALIGN MULTI-LEVEL CELL
    50.
    发明申请
    METHOD TO VERTICALLY ALIGN MULTI-LEVEL CELL 有权

    公开(公告)号：US20220021567A1

    公开(公告)日：2022-01-20

    申请号：US17381987

    申请日：2021-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Feng Lin

    IPC: H04L25/49 ,  H04L27/04 ,  G06F13/40 ,  G06F1/324 ,  G06F13/16 ,  H04L27/06 ,  H04L27/34

    Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

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