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    Semiconductor device
    41.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08373247B2

    公开(公告)日：2013-02-12

    申请号：US13029925

    申请日：2011-02-17

    申请人： Wataru Saito ,  Syotaro Uno ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

    发明人： Wataru Saito ,  Syotaro Uno ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

    IPC分类号： H01L29/06

    CPC分类号： H01L27/07 ,  H01L29/72

    摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.

    摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一导电类型的第二半导体区域，第一主电极，第二导电类型的第三半导体区域，第二主电极和 多个第二导电类型的嵌入式半导体区域。 第二半导体区域形成在第一半导体区域的第一主表面上。 第一主电极形成在与第一半导体区域的第一主表面相对的正面上。 第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。 第二主电极形成为结合到第三半导体区域。 嵌入式半导体区域设置在终端区域中。 沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    42.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120074461A1

    公开(公告)日：2012-03-29

    申请号：US13235302

    申请日：2011-09-16

    申请人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

    发明人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/331 ,  H01L29/739

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238

    摘要： According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

    摘要翻译： 根据实施例，半导体器件包括设置在第一半导体层上并包括第一柱和第二柱的第二半导体层。 第一控制电极设置在第二半导体层的沟槽中，第二控制电极设置在第二半导体层上并连接到第一控制电极。 除了第二控制电极下方的部分之外，在第二半导体层的表面上设置第一半导体区域。 第二半导体区域设置在第一半导体区域的表面上，第二半导体区域与第二控制电极下方的部分分开，第三半导体区域设置在第一半导体区域上。 第一主电极与第一半导体层电连接，第二主电极与第二和第三半导体区域电连接。

    SEMICONDUCTOR DEVICE
    43.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20120056262A1

    公开(公告)日：2012-03-08

    申请号：US13052028

    申请日：2011-03-18

    申请人： Wataru SAITO ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

    发明人： Wataru SAITO ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

    摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, an embedded electrode, a control electrode, a fourth semiconductor layer of the second conductivity type, a first main electrode, and a second main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The embedded electrode is provided in a first trench via a first insulating film. The first trench penetrates through the second semiconductor layer from a surface of the third semiconductor layer to reach the first semiconductor layer. The control electrode is provided above the embedded electrode via a second insulating film in the first trench. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench. The second trench penetrates through the second semiconductor layer from the surface of the third semiconductor layer to reach the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is provided in the second trench and connected to the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer. The embedded electrode is electrically connected to one of the second main electrode and the control electrode. A Schottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.

    摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二导电类型的第二半导体层，第一导电类型的第三半导体层，嵌入电极，控制电极，第四半导体 第二导电类型的层，第一主电极和第二主电极。 第二半导体层设置在第一半导体层上。 第三半导体层设置在第二半导体层上。 嵌入式电极经由第一绝缘膜设置在第一沟槽中。 第一沟槽从第三半导体层的表面穿过第二半导体层到达第一半导体层。 控制电极通过第一沟槽中的第二绝缘膜设置在嵌入电极的上方。 第四半导体层选择性地设置在第一半导体层中并连接到第二沟槽的下端。 第二沟槽从第三半导体层的表面穿过第二半导体层到达第一半导体层。 第一主电极电连接到第一半导体层。 第二主电极设置在第二沟槽中并连接到第二半导体层，第三半导体层和第四半导体层。 嵌入电极与第二主电极和控制电极中的一个电连接。 在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。

    POWER SEMICONDUCTOR DEVICE
    44.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权
    功率半导体器件

    公开(公告)号：US20110260243A1

    公开(公告)日：2011-10-27

    申请号：US13052893

    申请日：2011-03-21

    申请人： Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

    发明人： Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66734 ,  H01L29/7811

    摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type, a fourth semiconductor layer, a fifth semiconductor layer, a first and second main electrode, a first and second insulating film and a control electrode. The second and third layers are provided periodically on the first layer. The fourth layer is provided on the third layer. The fifth layer is selectively provided on the fourth layer. The first film is provided on sidewalls of a trench that reaches from a surface of the fifth layer to the second layer. The second film is provided closer to a bottom side of the trench than the first film and has a higher permittivity than the first film. The control electrode is embedded in the trench.

    摘要翻译： 根据一个实施例，功率半导体器件包括第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层，第四半导体层，第五半导体层， 第一和第二主电极，第一和第二绝缘膜和控制电极。 第二层和第三层周期性地设置在第一层上。 第四层设置在第三层上。 第五层选择性地设置在第四层上。 第一膜设置在从第五层的表面到第二层的沟槽的侧壁上。 第二膜比第一膜更靠近沟槽的底侧，并且具有比第一膜更高的介电常数。 控制电极嵌入沟槽中。

    Semiconductor device
    45.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07755138B2

    公开(公告)日：2010-07-13

    申请号：US12537219

    申请日：2009-08-06

    申请人： Wataru Saito ,  Syotaro Ono ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

    发明人： Wataru Saito ,  Syotaro Ono ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7806

    摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.

    摘要翻译： 本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分 层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。 源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

    Aliphatic polymer having ketone group and ether bonding in its main chain and resin composition containing the same
    46.
    发明授权
    Aliphatic polymer having ketone group and ether bonding in its main chain and resin composition containing the same 失效
    在其主链中具有酮基和醚键的脂族聚合物和含有它们的树脂组合物

    公开(公告)号：US07528215B2

    公开(公告)日：2009-05-05

    申请号：US10567907

    申请日：2004-04-30

    申请人： Taishi Shigematsu ,  Chikara Manabe ,  Masaki Hirakata ,  Kentaro Kishi ,  Miho Watanabe ,  Hiroyuki Watanabe

    发明人： Taishi Shigematsu ,  Chikara Manabe ,  Masaki Hirakata ,  Kentaro Kishi ,  Miho Watanabe ,  Hiroyuki Watanabe

    IPC分类号： C08G2/00 ,  C08G61/00 ,  C08G65/34 ,  D06P1/52

    CPC分类号： C08G65/34 ,  B82Y30/00 ,  C08G65/48 ,  C08K3/08

    摘要： The invention provides an aliphatic polymer having a ketone group and ether bonding in its main chain, characterized by comprising structural units represented by the Formula (1) and by the Formula (2). In the Formulae (1) and (2), Ra and Rb each independently represents a substituted or unsubstituted divalent aliphatic hydrocarbon group. Rc represents a substituted or unsubstituted divalent aliphatic hydrocarbon group having ether bonding in a terminal thereof, or a single bond. N1 represents an integer of 1 or more. N2 represents an integer of 0 or more. And, n1+n2 is in a range of 2 to 1000. The polymer preferably contains ether bonds and ketone groups in a ratio of 0.01 to 100. The polymer can be substantially comprised of a structural unit represented by the Formula (1) as a repeating unit. A resin composition containing as a component structural units represented by the Formula (1) is also provided. The resin composition may further comprise an electrically conductive powder.

    摘要翻译： 本发明提供了在其主链中具有酮基和醚键的脂族聚合物，其特征在于包括由式（1）和式（2）表示的结构单元。 在式（1）和（2）中，Ra和Rb各自独立地表示取代或未取代的二价脂族烃基。 Rc表示在其末端具有醚键的取代或未取代的二价脂族烃基或单键。 N1表示1以上的整数。 N2表示0以上的整数。 并且，n1 + n2在2〜1000的范围内。聚合物优选以0.01〜100的比例含有醚键和酮基。聚合物可以基本上由式（1）表示的结构单元作为 重复单位。 还提供了含有由式（1）表示的组分结构单元的树脂组合物。 树脂组合物还可以包含导电粉末。