公开(公告)号：US5981357A

公开(公告)日：1999-11-09

申请号：US877000

申请日：1997-06-16

申请人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

发明人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.

摘要翻译： 提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。 隔离过程产生具有增强的机械和电性能的硅台面。 通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。 通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。 图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。 图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

公开(公告)号：US5962914A

公开(公告)日：1999-10-05

申请号：US168761

申请日：1998-10-08

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/762 ,  H01L24/36

CPC分类号： H01L21/76213

摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

公开(公告)号：US5937310A

公开(公告)日：1999-08-10

申请号：US639758

申请日：1996-04-29

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76213 ,  Y10S438/981

摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

摘要翻译： 在不使用氮化硅的情况下形成自对准场氧化物隔离结构的方法。 该方法包括在半导体衬底的上表面上形成电介质。 半导体衬底的上表面包括相互横向相邻的有源区和隔离区。 在植入电介质的顶部上构图光致抗蚀剂层，以在有源区域上暴露植入电介质的区域。 然后通过植入电介质将氮注入有源区。 氮优选以0.5至2.0％的近似原子浓度引入半导体衬底。 在将氮气注入到半导体衬底中之后，剥离光致抗蚀剂层并除去注入电介质。 然后将晶片热氧化，使得具有第一厚度的场氧化物在隔离区上生长，并且在有源区上生长具有第二厚度的薄氧化物。 半导体衬底内的氮的存在阻碍了有源区中硅的氧化速率，使得薄氧化物的厚度基本上小于热氧化物的厚度。 在目前优选的实施例中，场氧化物的厚度为2,000至8,000埃，而薄氧化物的厚度小于300埃。

公开(公告)号：US5926693A

公开(公告)日：1999-07-20

申请号：US788376

申请日：1997-01-27

申请人： Mark I. Gardner ,  Fred N. Hause ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Fred N. Hause ,  Jon D. Cheek

IPC分类号： H01L27/07 ,  H01L27/088 ,  H01L21/00

CPC分类号： H01L27/0705 ,  H01L27/088

摘要： A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.

摘要翻译： 一种半导体工艺，其中沟槽晶体管形成在一对平面晶体管之间，使得沟槽晶体管的源极/漏极区域与平面晶体管的源极/漏极区域共享。 提供衬底，并且在衬底的上表面上形成第一和第二平面晶体管。 沟槽晶体管的栅极电介质在衬底的上表面下方垂直位移。 沟槽晶体管与第一平面晶体管共享第一共享源极/漏极结构，并且与第二平面晶体管共享第二共享源极/漏极结构。 沟槽晶体管的形成优选地包括以下步骤：将沟槽蚀刻到衬底中，热氧化沟槽的底部以形成沟槽栅极电介质，并用导电材料填充沟槽以形成沟槽栅极结构。 沟槽底部通过沟槽深度在衬底的上表面下方垂直移位。 沟槽深度优选地大于源极/漏极结构的结深度。 在一个实施例中，沟槽晶体管的形成还包括在沟槽底板的热氧化之前，在衬底的第一和第二沟槽区域内形成第一和第二层结构。 第一和第二沟槽层结构提供从位于沟槽底部下方的沟槽沟道区域分别延伸到第一和第二共享源极/漏极结构的导电路径。

公开(公告)号：US5849621A

公开(公告)日：1998-12-15

申请号：US666023

申请日：1996-06-19

申请人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823418 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823481 ,  Y10S257/90

摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

摘要翻译： 一种用于隔离半导体器件的方法，包括提供半导体衬底。 半导体衬底包括横向移位的源极/漏极区域和沟道区域。 第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。 第一和第二晶体管具有公共源极/漏极区域。 通过公共源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被分成电隔离的第一和第二源极/漏极区域，由此第一晶体管与 第二晶体管。

公开(公告)号：US5793089A

公开(公告)日：1998-08-11

申请号：US781443

申请日：1997-01-10

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a lateral surface to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. Preferably, the multi-layer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The oxide is grown upon the polysilicon to align a source/drain implant. Either before the source/drain implant or after the source/drain implant, the oxide and polysilicon partially consumed by the oxide is removed to provide a lateral surface to which an MDD implant aligns. A combination of etch stop, polysilicon spacer and grown possibly sacrificial oxide allows a greater ease by which multiple implants can be forwarded into junctions of either an NMOS or PMOS transistor.

公开(公告)号：US5679585A

公开(公告)日：1997-10-21

申请号：US746774

申请日：1996-11-15

申请人： Mark I. Gardner ,  Fred N. Hause ,  Derick J. Wristers ,  Dim-Lee Kwong

发明人： Mark I. Gardner ,  Fred N. Hause ,  Derick J. Wristers ,  Dim-Lee Kwong

IPC分类号： H01L21/285 ,  H01L21/283

CPC分类号： H01L21/28518 ,  Y10S438/909

摘要： An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.

摘要翻译： 提供了一种在半导体形貌上制造金属硅化物的方法。 该方法有利地在基本上较低的温度下进行退火循环。 通过采用高压退火室，在半导体形貌特别是在小的硅化物形成区域中实现了温度平衡。 较高的压力有助于确保加热的流动气体在要形成硅化物的较小几何形状上的热接触。 即使在相对较低的温度条件下，也可能在更高的压力下发生大量金属硅化物的形成。 较低的温度过程有助于确保预先存在的植入区域保持在其初始位置。 因此，目前的金属硅化物工艺和较低温度退火非常适合于避免杂质迁移问题，例如阈值偏移，寄生结电容增强和栅极氧化物降解。

公开(公告)号：US6137182A

公开(公告)日：2000-10-24

申请号：US137471

申请日：1998-08-20

申请人： Fred N. Hause ,  Mark I. Gardner ,  Robert Dawson

发明人： Fred N. Hause ,  Mark I. Gardner ,  Robert Dawson

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76816

摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.

摘要翻译： 一种用于形成层间接触的半导体工艺。 半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。 在电介质层上形成优选由多晶硅或氮化硅构成的边界层。 然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁 。 然后在环形侧壁上形成间隔结构，优选地，间隔物结构通过化学气相沉积间隔物材料形成，并且各向异性地蚀刻间隔物材料，以便在具有最小过氧化物的平面区域中刚好清除。 间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。 然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。 优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

公开(公告)号：US6118137A

公开(公告)日：2000-09-12

申请号：US925383

申请日：1997-09-08

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

IPC分类号： H01L23/528 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L23/528 ,  H01L2924/0002

摘要： The present invention advantageously provides a method for determining lithographic misalignment of a conductive element relative to a via. An electrically measured test structure is provided which is designed to have targeted via areas shifted from midlines of corresponding targeted conductor areas. Further, the test structure is designed to have a test pad that electrically communicates with the targeted via areas. Design specifications of the test structure require the midlines of the conductor areas to be offset from the via areas by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to each of the conductors while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a conductor is misaligned from its desired location. Using the electrical responses for all the conductors, it is possible to determine the direction and amount of misalignment.

摘要翻译： 本发明有利地提供了一种用于确定导电元件相对于通孔的光刻未对准的方法。 提供了一种电测试的测试结构，其被设计成具有从相应的目标导体区域的中线偏移的目标通孔区域。 此外，测试结构被设计成具有与目标通孔区域电连通的测试垫。 测试结构的设计规范要求导体区域的中线通过不同的距离偏离通孔区域。 上述方法涉及处理设计的测试结构。 然后可以将电信号施加到每个导体，同时它也被施加到测试垫。 所产生的电响应应与导体与其所需位置不对准的距离成正比。 使用所有导体的电响应，可以确定未对准的方向和量。

公开(公告)号：US6051863A

公开(公告)日：2000-04-18

申请号：US975582

申请日：1997-11-21

申请人： Fred N. Hause ,  Mark I. Gardner ,  Charles E. May

发明人： Fred N. Hause ,  Mark I. Gardner ,  Charles E. May

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L29/665

摘要： A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom. Thus, when a silicide-forming metal is deposited, the metal accumulates at the peak of each spacer and is inhibited from being deposited upon the lower portions of the spacers, thereby preventing silicide bridging between the gate conductor and ensuing source/drain regions of the transistor.

摘要翻译： 提供了一种用于制造具有相对侧壁表面的晶体管栅极导体的方法，在该侧壁表面上形成有电介质间隔物，使得当栅极导体侧壁表面接近栅极导体的基极时，间隔物轮廓基本上逐渐朝着相邻的栅极导体侧壁表面逐渐变细。 更具体地说，侧壁间隔物的形成涉及各向异性蚀刻在钝化源的存在下横跨半导体形貌沉积的电介质材料，以在介电材料的一部分上形成钝化剂。 钝化剂主要积聚在电介质材料的侧表面的上部。 使用在所有方向上以相同速率发生的各向同性蚀刻来蚀刻未被钝化剂完全覆盖的介电材料的部分。 所得的间隔物具有从顶部到底部减小的变化的厚度。 因此，当沉积硅化物形成金属时，金属在每个间隔物的峰处积聚，并且被抑制沉积在间隔物的下部，从而防止栅极导体与随后的源极/漏极区之间的硅化物桥接 晶体管。