公开(公告)号：US06459619B1

公开(公告)日：2002-10-01

申请号：US09986081

申请日：2001-11-07

申请人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for-each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

摘要翻译： 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且每个存储器单元的阈值电压被管理在所选存储器块中的每个字线。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US06842376B2

公开(公告)日：2005-01-11

申请号：US10638491

申请日：2003-08-12

申请人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/02 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

摘要翻译： 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US07529126B2

公开(公告)日：2009-05-05

申请号：US11472993

申请日：2006-06-23

申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.

摘要翻译： 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1iA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

公开(公告)号：US07467339B2

公开(公告)日：2008-12-16

申请号：US11329229

申请日：2006-01-11

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/021 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/3187 ,  G06F11/24 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/5004

摘要： A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

公开(公告)号：US07085157B2

公开(公告)日：2006-08-01

申请号：US10805365

申请日：2004-03-22

申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.

摘要翻译： 一种用于通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入和降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1AA的恒定电流，并且通过约1μA的恒定电流放电位线以使存储器单元中的电流流动。

公开(公告)号：US07000160B2

公开(公告)日：2006-02-14

申请号：US10083399

申请日：2002-02-27

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

IPC分类号： G01R31/28

CPC分类号： G11C29/021 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/3187 ,  G06F11/24 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/5004

摘要： A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

公开(公告)号：US5047825A

公开(公告)日：1991-09-10

申请号：US485598

申请日：1990-02-27

申请人： Kazuo Yasaka ,  Yutaka Shinagawa ,  Toru Miyamoto

发明人： Kazuo Yasaka ,  Yutaka Shinagawa ,  Toru Miyamoto

IPC分类号： H01L21/768 ,  H01L27/112

CPC分类号： H01L27/112 ,  H01L21/76886

摘要： In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed. Concretely, the method comprises the steps of providing selector switch elements which serve to select decode signal lines in accordance with address signals received from pairs of complementary address signal lines, each pair including a true line and a bar line, in a decoder forming region of a semiconductor substrate; providing a conductor film which is connected to input terminals of the selector switch elements and which is extended under regions for forming the true lines and the bar lines; providing an interlayer insulator film on the selector switch elements and the conductor film; forming contact holes in the interlayer insulator film on the conductor film so as to reach the conductor film; and connecting either of the true lines and the bar lines to the conductor film through the contact holes.

摘要翻译： 在诸如其中设置有指令程序的ROM的半导体集成电路器件中，其中用于选择字线的顺序根据书面信息而各不相同; 公开了一种制造方法，其可以在确定指令程序之后缩短生产过程或者在不增加制造步骤的情况下解码解码器的电路布置。 具体地说，该方法包括以下步骤：提供选择器开关元件，该选择器开关元件用于根据从补码地址信号线对中接收的地址信号选择解码信号线，每对互补地址信号线包括真线和条线， 半导体衬底; 提供连接到选择器开关元件的输入端并在用于形成真线和条线的区域下延伸的导体膜; 在选择器开关元件和导体膜上提供层间绝缘膜; 在导体膜上的层间绝缘膜中形成接触孔，以到达导体膜; 并且通过接触孔将真线和条线之一连接到导体膜。

公开(公告)号：US20090129173A1

公开(公告)日：2009-05-21

申请号：US12269098

申请日：2008-11-12

申请人： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C8/00 ,  G11C7/06

CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行流水线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

公开(公告)号：US07848177B2

公开(公告)日：2010-12-07

申请号：US12269098

申请日：2008-11-12

申请人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行管线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

公开(公告)号：US4910162A

公开(公告)日：1990-03-20

申请号：US361347

申请日：1989-06-05

申请人： Kazuo Yasaka ,  Yutaka Shinagawa ,  Toru Miyamoto

发明人： Kazuo Yasaka ,  Yutaka Shinagawa ,  Toru Miyamoto

IPC分类号： G11C17/00 ,  G11C16/06 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/112 ,  H01L21/76886

摘要： In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed. Concretely, the method comprises the steps of providing selector switch elements which serve to select decode signal lines in accordance with address signals received from pairs of complementary address signal lines, each pair including a true line and a bar line, in a decoder forming region of a semiconductor substrate; providing a conductor film which is connected to input terminals of the selector switch elements and which is extended under regions for forming the true lines and the bar lines; providing an interlayer insulator film on the selector switch elements and the conductor film; forming contact holes in the interlayer insulator film on the conductor film so as to reach the conductor film; and connecting either of the true lines and the bar lines to the conductor film through the contact holes.

摘要翻译： 在诸如其中设置有指令程序的ROM的半导体集成电路器件中，其中用于选择字线的顺序根据书面信息而各不相同; 公开了一种制造方法，其可以在确定指令程序之后缩短生产过程或者在不增加制造步骤的情况下解码解码器的电路布置。 具体地说，该方法包括以下步骤：提供选择器开关元件，该选择器开关元件用于根据从补码地址信号线对中接收的地址信号选择解码信号线，每对互补地址信号线包括真线和条线， 半导体衬底; 提供连接到选择器开关元件的输入端并在用于形成真线和条线的区域下延伸的导体膜; 在选择器开关元件和导体膜上提供层间绝缘膜; 在导体膜上的层间绝缘膜中形成接触孔，以到达导体膜; 并且通过接触孔将真线和条线之一连接到导体膜。