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    METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS IN A POINT-TO-POINT INTERCONNECT ARCHITECTURE
    41.
    发明申请
    METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS IN A POINT-TO-POINT INTERCONNECT ARCHITECTURE 失效
    在点对点互连架构中过滤SNOOP要求的方法和装置

    公开(公告)号：US20080133845A1

    公开(公告)日：2008-06-05

    申请号：US12035085

    申请日：2008-02-21

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831 ,  G06F12/084 ,  Y02D10/13

    摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

    摘要翻译： 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。 该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于在多处理器计算环境中从专用存储器写入源接收窥探请求。 每个存储器写入源以点对点互连方式直接连接到与所有其他处理单元相关联的所有其他窥探滤波器设备的专用输入端口。 每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，该多个专用输入端口适于同时滤除从相应专用存储器写入源接收到的窥探请求，并将这些请求的子集转发到其相关联的处理单元。

    Snoop filter for filtering snoop requests
    43.
    发明授权
    Snoop filter for filtering snoop requests 有权
    用于过滤窥探请求的Snoop过滤器

    公开(公告)号：US08677073B2

    公开(公告)日：2014-03-18

    申请号：US13587420

    申请日：2012-08-16

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

    IPC分类号： G06F13/28 ,  G06F12/00

    CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F2212/507 ,  Y02D10/13

    摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

    摘要翻译： 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。 该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。 每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求 写入源并将这些请求的子集转发到其相关联的处理单元。

    TLB EXCLUSION RANGE
    45.
    发明申请
    TLB EXCLUSION RANGE 有权
    TLB排除范围

    公开(公告)号：US20130024648A1

    公开(公告)日：2013-01-24

    申请号：US13618730

    申请日：2012-09-14

    申请人： Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Jon K. Kriegel ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    发明人： Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Jon K. Kriegel ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/652 ,  G06F2212/654

    摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

    摘要翻译： 提供了一种访问存储器的系统和方法。 该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有 一个或多个位被设置为从页面排除存储器范围。

    STORE-OPERATE-COHERENCE-ON-VALUE
    47.
    发明申请
    STORE-OPERATE-COHERENCE-ON-VALUE 有权
    存储操作相关值

    公开(公告)号：US20110179229A1

    公开(公告)日：2011-07-21

    申请号：US12986652

    申请日：2011-01-07

    申请人： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    发明人： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  Y02D10/13

    摘要： A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

    摘要翻译： 一种用于在包括多个处理器和至少一个高速缓冲存储器设备的并行计算环境中执行各种存储操作指令的系统，方法和计算机程序产品。 系统中的队列从处理器接收存储操作指令，该指令指定在哪个条件下调用高速缓存一致性操作。 系统中的硬件单元运行接收到的存储操作指令。 硬件单元评估运行接收到的存储操作指令的结果是否满足条件。 如果结果满足条件，则硬件单元调用与接收到的存储操作指令相关联的高速缓存存储器地址的高速缓存一致性操作。 否则，硬件单元不会调用高速缓存存储器设备上的高速缓存一致性操作。

    Multiple node remote messaging
    48.
    发明授权
    Multiple node remote messaging 有权
    多节点远程消息传递

    公开(公告)号：US07788334B2

    公开(公告)日：2010-08-31

    申请号：US11768784

    申请日：2007-06-26

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Valentina Salapura ,  Burkhard Steinmacher-Burow ,  Pavlos Vranas

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Valentina Salapura ,  Burkhard Steinmacher-Burow ,  Pavlos Vranas

    IPC分类号： G06F15/167 ,  G06F13/28

    CPC分类号： G06F15/16

    摘要： A method for passing remote messages in a parallel computer system formed as a network of interconnected compute nodes includes that a first compute node (A) sends a single remote message to a remote second compute node (B) in order to control the remote second compute node (B) to send at least one remote message. The method includes various steps including controlling a DMA engine at first compute node (A) to prepare the single remote message to include a first message descriptor and at least one remote message descriptor for controlling the remote second compute node (B) to send at least one remote message, including putting the first message descriptor into an injection FIFO at the first compute node (A) and sending the single remote message and the at least one remote message descriptor to the second compute node (B).

    摘要翻译： 在形成为互连的计算节点的网络的并行计算机系统中传递远程消息的方法包括：第一计算节点（A）将单个远程消息发送到远程第二计算节点（B），以便控制远程第二计算 节点（B）发送至少一个远程消息。 该方法包括各种步骤，包括在第一计算节点（A）处控制DMA引擎以准备单个远程消息以包括第一消息描述符和至少一个远程消息描述符，用于控制远程第二计算节点（B）至少发送 一个远程消息，包括将第一消息描述符放在第一计算节点（A）的注入FIFO中，并将单个远程消息和至少一个远程消息描述符发送到第二计算节点（B）。

    NOVEL SNOOP FILTER FOR FILTERING SNOOP REQUESTS
    49.
    发明申请
    NOVEL SNOOP FILTER FOR FILTERING SNOOP REQUESTS 失效
    用于过滤SNOOP要求的新SNOOP过滤器

    公开(公告)号：US20090006770A1

    公开(公告)日：2009-01-01

    申请号：US12113262

    申请日：2008-05-01

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F2212/507 ,  Y02D10/13

    摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

    摘要翻译： 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。 该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。 每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求 写入源并将这些请求的子集转发到其相关联的处理单元。

    EXTENDED WRITE COMBINING USING A WRITE CONTINUATION HINT FLAG
    50.
    发明申请
    EXTENDED WRITE COMBINING USING A WRITE CONTINUATION HINT FLAG 失效
    使用写持续提示标签扩展写入组合

    公开(公告)号：US20090006605A1

    公开(公告)日：2009-01-01

    申请号：US11768593

    申请日：2007-06-26

    申请人： Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht ,  Pavlos Vranas

    发明人： Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht ,  Pavlos Vranas

    IPC分类号： G06F17/30 ,  G06F15/173

    CPC分类号： H04L49/9021 ,  G06F12/0862 ,  H04L49/90

    摘要： A computing apparatus for reducing the amount of processing in a network computing system which includes a network system device of a receiving node for receiving electronic messages comprising data. The electronic messages are transmitted from a sending node. The network system device determines when more data of a specific electronic message is being transmitted. A memory device stores the electronic message data and communicating with the network system device. A memory subsystem communicates with the memory device. The memory subsystem stores a portion of the electronic message when more data of the specific message will be received, and the buffer combines the portion with later received data and moves the data to the memory device for accessible storage.

    摘要翻译： 一种用于减少网络计算系统中的处理量的计算装置，其包括用于接收包括数据的电子消息的接收节点的网络系统设备。 从发送节点发送电子消息。 网络系统设备确定何时正在发送特定电子消息的更多数据。 存储装置存储电子消息数据并与网络系统装置进行通信。 存储器子系统与存储器件通信。 当更多的特定消息的数据将被接收时，存储器子系统存储电子消息的一部分，并且缓冲器将该部分与稍后接收的数据组合，并将数据移动到存储器装置以进行存取。