公开(公告)号：US08716813B2

公开(公告)日：2014-05-06

申请号：US13556333

申请日：2012-07-24

申请人： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/02164 ,  H01L21/02697 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/518

摘要： A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.

摘要翻译： 场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层， 与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

公开(公告)号：US08895384B2

公开(公告)日：2014-11-25

申请号：US13293210

申请日：2011-11-10

申请人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

发明人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364

摘要： A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.

摘要翻译： 提供了具有通道材料的金属栅极结构及其制造方法。 该方法包括在衬底上形成虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁结构。 该方法还包括去除伪栅极结构以形成由侧壁结构限定的第一沟槽和第二沟槽。 该方法还包括在第一沟槽和第二沟槽中的衬底上形成沟道材料。 该方法还包括在第一沟槽被掩蔽的同时从第二沟槽去除沟道材料。 该方法还包括用栅极材料填充第一沟槽和第二沟槽的剩余部分。

公开(公告)号：US08647972B1

公开(公告)日：2014-02-11

申请号：US13618255

申请日：2012-09-14

申请人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

发明人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

摘要： Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

摘要翻译： 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个或多个衬底和绝缘体，其包括限定沟槽的基底和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其他金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US20130087856A1

公开(公告)日：2013-04-11

申请号：US13253430

申请日：2011-10-05

申请人： Claude Ortolland ,  Unoh Kwon ,  Kota V.R.M. Murali ,  Edward J. Nowak ,  Rajan Kumar Pandey

发明人： Claude Ortolland ,  Unoh Kwon ,  Kota V.R.M. Murali ,  Edward J. Nowak ,  Rajan Kumar Pandey

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545

摘要： A CMOS structure is formed on a semiconductor substrate that includes first and second regions having an nFET and a pFET respectively formed thereon. Each nFET and pFET device is provided with a gate, a source and drain, and a channel formed on the substrate. A high permittivity dielectric layer formed on top of the channel is superimposed to the permittivity dielectric layer. The pFET gate includes a thick metal nitride alloy layer or rich metal nitride alloy or carbon metal nitride layer that provides a controlled WF. Superimposed to the permittivity dielectric layer, the nFET gate is provided with a thin metal nitride alloy layer, enabling to control the WF. A metal deposition is formed on top of the respective nitride layers. The gate last approach characterized by having a high thermal budget smaller than 500° C. used for post metal deposition, following the dopant activation anneal.

摘要翻译： 在包括分别在其上形成有nFET和pFET的第一和第二区域的半导体衬底上形成CMOS结构。 每个nFET和pFET器件设置有栅极，源极和漏极以及形成在衬底上的沟道。 形成在通道顶部的高介电常数介电层叠加到介电常数介电层上。 pFET栅极包括提供受控WF的厚金属氮化物合金层或富金属氮化物合金或碳金属氮化物层。 与介电常数介电层叠加，nFET栅极设置有薄的金属氮化物合金层，能够控制WF。 在各个氮化物层的顶部上形成金属沉积。 门最后一种方法的特征在于，在掺杂剂激活退火之后，具有小于500℃的高热预算用于后金属沉积。

公开(公告)号：US08716118B2

公开(公告)日：2014-05-06

申请号：US13345295

申请日：2012-01-06

申请人： Takashi Ando ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

摘要： A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.

摘要翻译： 晶体管包括位于半导体层上的半导体层和栅极结构。 栅极结构包括第一介电层。 第一介电层包括掺杂区域和掺杂区域下面的未掺杂区域。 第二电介质层位于第一电介质层上，第一金属氮化物层位于第二电介质层上。 第一介电层的掺杂区域包括来自第二介电层的掺杂剂。 半导体层中的源极和漏极区位于栅极结构的相对侧上。

公开(公告)号：US08659077B1

公开(公告)日：2014-02-25

申请号：US13615343

申请日：2012-09-13

申请人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

发明人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC分类号： H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

摘要： Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

摘要翻译： 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个通道结构，该通道结构包括限定沟槽的底座和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其他金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US20130256802A1

公开(公告)日：2013-10-03

申请号：US13430755

申请日：2012-03-27

申请人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

发明人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC分类号： H01L27/088 ,  H01L21/283

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。

公开(公告)号：US20130168776A1

公开(公告)日：2013-07-04

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US20120112290A1

公开(公告)日：2012-05-10

申请号：US12942097

申请日：2010-11-09

申请人： Henry K. Utomo ,  Unoh Kwon ,  Dimitri Anastassios Levedakis ,  Ravikumar Ramachandran ,  Viraj Yashawant Sardesai ,  Rajasekhar Venigalla

发明人： Henry K. Utomo ,  Unoh Kwon ,  Dimitri Anastassios Levedakis ,  Ravikumar Ramachandran ,  Viraj Yashawant Sardesai ,  Rajasekhar Venigalla

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.

摘要翻译： 公开了一种替代金属栅极（RMG）场效应晶体管的结构和方法。 硅化物区域形成在升高的源极 - 漏极（RSD）结构上。 硅化物区域在用于在更换之前暴露栅极的CMP工艺期间形成化学机械抛光（CMP）停止层。 然后在金属触点的形成中施加和蚀刻保护层。

公开(公告)号：US08716088B2

公开(公告)日：2014-05-06

申请号：US13534573

申请日：2012-06-27

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.