公开(公告)号：US20240428872A1

公开(公告)日：2024-12-26

申请号：US18800552

申请日：2024-08-12

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

公开(公告)号：US20240143501A1

公开(公告)日：2024-05-02

申请号：US18494841

申请日：2023-10-26

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Luigi Pilolli ,  Liang Yu ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Biagio Iorio

IPC: G06F12/02 ,  G06F1/28

CPC classification number: G06F12/0246 ,  G06F1/28

Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.

公开(公告)号：US11662939B2

公开(公告)日：2023-05-30

申请号：US16946869

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1668

Abstract: A processing device in a memory sub-system determines whether to check a status of one or more memory dies of the memory device and sends a multi-unit status command to the memory device, the multi-unit status command specifying a plurality of memory units associated with the one or more memory dies of the memory device. The processing device further receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

公开(公告)号：US11556251B2

公开(公告)日：2023-01-17

申请号：US17187066

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Dheeraj Srinivasan ,  Terry M. Grunzke

IPC: G06F3/06 ,  G06F12/0811

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

公开(公告)号：US11334265B2

公开(公告)日：2022-05-17

申请号：US16914547

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0811

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.

公开(公告)号：US20220083241A1

公开(公告)日：2022-03-17

申请号：US16948426

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Walter Di Francesco ,  Yuanhang Cao ,  Luca De Santis ,  Fumin Gu

IPC: G06F3/06

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

公开(公告)号：US10832779B2

公开(公告)日：2020-11-10

申请号：US16530100

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

IPC: G11C16/08 ,  G11C16/12 ,  G06F3/06 ,  G11C8/08 ,  G11C16/14 ,  G11C16/30

Abstract: Apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

公开(公告)号：US10698624B2

公开(公告)日：2020-06-30

申请号：US16178366

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0811

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.

公开(公告)号：US10423350B2

公开(公告)日：2019-09-24

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10388379B2

公开(公告)日：2019-08-20

申请号：US15531283

申请日：2017-03-21

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/12 ,  G11C8/08 ,  G11C16/14 ,  G11C16/30

Abstract: An apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.