公开(公告)号：US20250054531A1

公开(公告)日：2025-02-13

申请号：US18930833

申请日：2024-10-29

Applicant: Micron Technology, Inc.

Inventor： Tong Liu ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

公开(公告)号：US20240329840A1

公开(公告)日：2024-10-03

申请号：US18607026

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Giorgio Servalli ,  Marcello Mariani

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: Methods, systems, and devices for memory array configuration for shared word lines are described. A memory array of a memory device may include shared (e.g., shorted) word lines. The memory array may include multiple memory cells, word lines, rows of transistors, and digit lines. Each transistor of the rows of transistors may be coupled with a respective memory cell and includes a connection between a first word line, a second word line, and a gate terminal of a transistor. Additionally, each digit line may be coupled with respective terminals of respective transistors of alternating rows of transistors including a first subset of alternating rows and a second subset of alternating rows that are exclusive from each other. The transistors may be configured according to a first configuration including two digit lines overlapping each transistor or a second configuration including a single digit line overlapping each transistor.

公开(公告)号：US20240276736A1

公开(公告)日：2024-08-15

申请号：US18589134

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Fatma Arzum Simsek-Ege

IPC: H10B53/30 ,  G11C11/22 ,  H10B51/20 ,  H10B51/30 ,  H10B51/40 ,  H10B53/20 ,  H10B53/40

CPC classification number: H10B53/30 ,  G11C11/2255 ,  H10B51/20 ,  H10B51/30 ,  H10B51/40 ,  H10B53/20 ,  H10B53/40

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

公开(公告)号：US20240221806A1

公开(公告)日：2024-07-04

申请号：US18408252

申请日：2024-01-09

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/18

CPC classification number: G11C7/12 ,  G11C7/1039 ,  G11C7/18

Abstract: Methods, systems, and devices for signal development circuitry layouts in a memory device are described. A memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. For example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. Formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.

公开(公告)号：US20230350582A1

公开(公告)日：2023-11-02

申请号：US17730777

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir Javanifard ,  Daniele Vimercati

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

公开(公告)号：US11727981B2

公开(公告)日：2023-08-15

申请号：US17369873

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US11705185B2

公开(公告)日：2023-07-18

申请号：US17362280

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/408 ,  G05F3/26 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G05F3/262 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4085

Abstract: Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

公开(公告)号：US20230186965A1

公开(公告)日：2023-06-15

申请号：US18084884

申请日：2022-12-20

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

Abstract: Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

公开(公告)号：US20230011345A1

公开(公告)日：2023-01-12

申请号：US17369873

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/06

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US20220415382A1

公开(公告)日：2022-12-29

申请号：US17362306

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06

Abstract: Methods, systems, and devices for sensing techniques for differential memory cells are described. A method may include selecting a pair of memory cells that comprise a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line for a read operation, the pair of memory cells storing one bit of information. The method may further include applying a first voltage to a plate line coupled with the first memory cell and the second memory cell and applying a second voltage to a select line to couple the first digit line and the second digit line with a sense amplifier. The amplifier may sense a logic state of the pair of memory cells based on a difference between a third voltage of the first digit line and a fourth voltage of the second digit line.