公开(公告)号：US11651825B2

公开(公告)日：2023-05-16

申请号：US17227977

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Hongmei Wang ,  Robert J. Gleixner

IPC: G06F7/58 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/102 ,  G06F7/588 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3409

Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

公开(公告)号：US11587635B2

公开(公告)日：2023-02-21

申请号：US17013089

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Nevil N. Gajera ,  Mingdong Cui ,  Fabio Pellizzer

IPC: G11C29/38 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

公开(公告)号：US11217322B2

公开(公告)日：2022-01-04

申请号：US16990114

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Hongmei Wang

IPC: G11C29/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  G11C29/52

Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

公开(公告)号：US20210183440A1

公开(公告)日：2021-06-17

申请号：US16717944

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang

IPC: G11C13/00 ,  G11C8/16

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

公开(公告)号：US20210183421A1

公开(公告)日：2021-06-17

申请号：US17085154

申请日：2020-10-30

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Jin Seung Son ,  Andrea Ghetti

IPC: G11C8/08 ,  G11C7/12

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

公开(公告)号：US20210111226A1

公开(公告)日：2021-04-15

申请号：US17130215

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Lorenzo Fratin ,  Hongmei Wang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L21/66

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

公开(公告)号：US10910438B2

公开(公告)日：2021-02-02

申请号：US16400943

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Lorenzo Fratin ,  Hongmei Wang

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

公开(公告)号：US20200372966A1

公开(公告)日：2020-11-26

申请号：US16990114

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Hongmei Wang

IPC: G11C29/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  G11C29/52

Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

公开(公告)号：US10650891B2

公开(公告)日：2020-05-12

申请号：US16419895

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Rajesh Kamana ,  Hongmei Wang ,  Shawn D. Lyonsmith ,  Ervin T. Hill ,  Zengtao T. Liu ,  Marlon W. Hug

IPC: G11C13/04 ,  G11C29/02 ,  G11C13/00 ,  G11C7/00 ,  G11C29/50 ,  G11C29/56

Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

公开(公告)号：US20190341122A1

公开(公告)日：2019-11-07

申请号：US16419885

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Rajesh Kamana ,  Hongmei Wang ,  Shawn D. Lyonsmith ,  Ervin T. Hill ,  Zengtao T. Liu ,  Marlon W. Hug

IPC: G11C29/50 ,  G11C29/56 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L21/66

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.