公开(公告)号：US20210202710A1

公开(公告)日：2021-07-01

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20210183651A1

公开(公告)日：2021-06-17

申请号：US17101950

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C01G41/00 ,  C23C16/28

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US20200328348A1

公开(公告)日：2020-10-15

申请号：US16382026

申请日：2019-04-11

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Tao D. Nguyen ,  John Mark Meldrim ,  Aaron K. Belsher

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.

公开(公告)号：US10731273B2

公开(公告)日：2020-08-04

申请号：US16436501

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： John Mark Meldrim ,  Yushi Hu ,  Yongjun Jeff Hu ,  Everett Allen McTeer

IPC: C30B29/38 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11582 ,  C30B23/02 ,  C30B25/02 ,  H01L21/225 ,  H01L27/11524 ,  H01L27/1157

Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.

公开(公告)号：US20200211843A1

公开(公告)日：2020-07-02

申请号：US16235765

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C23C16/28 ,  C01G41/00

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US10700091B2

公开(公告)日：2020-06-30

申请号：US16431527

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/1157

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US10573661B2

公开(公告)日：2020-02-25

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US10546848B2

公开(公告)日：2020-01-28

申请号：US16398433

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

IPC: G11C11/34 ,  H01L27/02 ,  H01L21/82 ,  H01L27/12 ,  G11C5/06 ,  H01L23/532

Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190333933A1

公开(公告)日：2019-10-31

申请号：US16430713

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

公开(公告)号：US10361216B2

公开(公告)日：2019-07-23

申请号：US15710432

申请日：2017-09-20

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.