公开(公告)号：US20210358940A1

公开(公告)日：2021-11-18

申请号：US15931421

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Andrew Li ,  Haoyu Li ,  Matthew J. King ,  Wei Yeeng Ng ,  Yongjun Jeff Hu

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/306 ,  H01L21/283

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210351127A1

公开(公告)日：2021-11-11

申请号：US17385299

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L21/762

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

公开(公告)号：US11121146B2

公开(公告)日：2021-09-14

申请号：US16159955

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/11573 ,  H01L27/11578 ,  H01L21/768 ,  H01L21/762 ,  H01L27/1157 ,  H01L27/11575

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

公开(公告)号：US20210057428A1

公开(公告)日：2021-02-25

申请号：US16550238

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US20210043644A1

公开(公告)日：2021-02-11

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US10658380B2

公开(公告)日：2020-05-19

申请号：US16160146

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US10600682B2

公开(公告)日：2020-03-24

申请号：US16172218

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3105 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US10269625B1

公开(公告)日：2019-04-23

申请号：US15857197

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US09679964B2

公开(公告)日：2017-06-13

申请号：US14853793

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew J. King

IPC: H01L21/76 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/74

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

公开(公告)号：US20140159132A1

公开(公告)日：2014-06-12

申请号：US13706532

申请日：2012-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Daycock ,  Matthew J. King ,  Christopher J. Larsen

IPC: H01L29/51 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4991

Abstract: Memory arrays and their formation are disclosed. The formation of one such memory array includes forming first and second spacers respectively adjacent to sidewalls of first and second conductors so that the first and second spacers extend into an opening between the first and second conductors and terminate above bottoms of the first and second conductors, and closing the opening with a material that extends between the first and second spacers so that an air gap is formed in the closed opening.

Abstract translation: 公开了存储器阵列及其形成。 一个这样的存储器阵列的形成包括分别与第一和第二导体的侧壁相邻地形成第一和第二间隔物，使得第一和第二间隔物延伸到第一和第二导体之间的开口中并终止在第一和第二导体的底部之上， 并且用在第一和第二间隔件之间延伸的材料封闭开口，使得在封闭的开口中形成气隙。